| /xsrc/external/mit/MesaLib/dist/src/intel/compiler/ |
| H A D | brw_ir_performance.h | 65 unsigned latency; member in struct:brw::performance
72 * width of the program and its latency estimate in cases where
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| H A D | brw_schedule_instructions.cpp | 42 * compute a DAG of the dependencies (RAW ordering with latency, WAW
43 * ordering with latency, WAR ordering), and make a list of the DAG heads.
78 int latency; member in class:schedule_node
87 * This is the sum of the instruction's latency plus the maximum delay of
127 this->latency = 1 * chans * math_latency;
130 this->latency = 2 * chans * math_latency;
136 this->latency = 3 * chans * math_latency;
141 this->latency = 4 * chans * math_latency;
144 this->latency = 8 * chans * math_latency;
148 /* minimum latency, ma
1046 add_dep(schedule_node * before,schedule_node * after,int latency) argument
[all...] |
| H A D | brw_fs_generator.cpp | 2778 loop_count, perf.latency,
2810 loop_count, perf.latency,
2820 stats->cycles = perf.latency;
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| H A D | brw_vec4_generator.cpp | 2251 stage_abbrev, before_size / 16, loop_count, perf.latency,
2271 loop_count, perf.latency, spill_count,
2278 stats->cycles = perf.latency;
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| H A D | brw_ir_performance.cpp | 240 * latency equal to ld followed by another computation with a
243 * the latency of the accumulator computation offset accordingly.
1626 p.latency = elapsed;
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| /xsrc/external/mit/MesaLib.old/dist/src/intel/compiler/ |
| H A D | brw_schedule_instructions.cpp | 41 * compute a DAG of the dependencies (RAW ordering with latency, WAW
42 * ordering with latency, WAR ordering), and make a list of the DAG heads.
76 int latency; member in class:schedule_node
85 * This is the sum of the instruction's latency plus the maximum delay of
125 this->latency = 1 * chans * math_latency;
128 this->latency = 2 * chans * math_latency;
134 this->latency = 3 * chans * math_latency;
139 this->latency = 4 * chans * math_latency;
142 this->latency = 8 * chans * math_latency;
146 /* minimum latency, ma
976 add_dep(schedule_node * before,schedule_node * after,int latency) argument
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/amd/compiler/ |
| H A D | aco_statistics.cpp | 98 int latency; member in struct:aco::perf_info
369 cur_cycle += program->chip_class >= GFX10 ? 1 : perf.latency;
395 int latency = MAX3(wait_info.exp, wait_info.lgkm, wait_info.vm); local in function:aco::BlockCycleEstimator::add
396 int32_t result_available = start + MAX2(perf.latency, latency);
472 double latency = 0; local in function:aco::collect_preasm_stats
522 latency += block_est.cur_cycle * iter;
536 parallelism = MIN2(parallelism, latency / usage[i]);
538 double waves_per_cycle = 1.0 / latency * parallelism;
547 program->statistics[statistic_latency] = round(latency);
[all...] |
| /xsrc/external/mit/libxcb/dist/ |
| H A D | README.md | 8 - latency hiding: batch several requests and wait for the replies later
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| /xsrc/external/mit/MesaLib.old/dist/src/broadcom/compiler/ |
| H A D | qpu_schedule.c | 65 uint32_t latency; member in struct:schedule_node
541 /* Schedule texture read results collection late to hide latency. */
554 /* Schedule texture read setup early to hide their latency better. */
878 /* Apply some huge latency between texture fetch requests and getting
916 uint32_t latency = 1; local in function:instruction_latency
920 return latency;
923 latency = MAX2(latency,
929 latency = MAX2(latency,
983 uint32_t latency = instruction_latency(node, child); local in function:mark_instruction_scheduled
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/broadcom/compiler/ |
| H A D | qpu_schedule.c | 65 uint32_t latency; member in struct:schedule_node
648 /* Schedule texture read results collection late to hide latency. */
657 /* Schedule texture read setup early to hide their latency better. */
1320 /* Apply some huge latency between texture fetch requests and getting
1361 uint32_t latency = 1; local in function:instruction_latency
1365 return latency;
1368 latency = MAX2(latency,
1375 latency = MAX2(latency,
1436 uint32_t latency = instruction_latency(devinfo, node, child); local in function:mark_instruction_scheduled
[all...] |
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/vc4/ |
| H A D | vc4_qpu_schedule.c | 65 uint32_t latency; member in struct:schedule_node
532 /* Schedule texture read results collection late to hide latency. */
541 /* Schedule texture read setup early to hide their latency better. */
713 /* Apply some huge latency between texture fetch requests and getting
813 uint32_t latency = instruction_latency(node, child); local in function:mark_instruction_scheduled
816 time + latency);
970 * handle A/B register file write latency)
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| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/vc4/ |
| H A D | vc4_qpu_schedule.c | 65 uint32_t latency; member in struct:schedule_node
532 /* Schedule texture read results collection late to hide latency. */
541 /* Schedule texture read setup early to hide their latency better. */
713 /* Apply some huge latency between texture fetch requests and getting
813 uint32_t latency = instruction_latency(node, child); local in function:mark_instruction_scheduled
816 time + latency);
970 * handle A/B register file write latency)
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| /xsrc/external/mit/MesaLib/dist/docs/relnotes/ |
| H A D | 20.1.0.rst | 414 - pan/bi: Add high-latency property for classes
3665 - freedreno/ir3: don't hide latency when there is none to hide
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| H A D | 20.2.0.rst | 4450 - radv: disable CPU caching for IBS to reduce fetch latency
4454 - radv: disable CPU caching for the upload BO to reduce fetch latency
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| H A D | 21.1.0.rst | 4785 - aco: add latency and inverse throughput statistics
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| H A D | 21.2.0.rst | 3336 - intel/compiler: Track latency/perf of LSC fences
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