| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/a6xx/ |
| fd6_zsa.c | 50 * lrz-test. See:
60 /* nothing to do for LRZ, but for stencil test when stencil-
61 * write is enabled, we need to disable lrz-test, since
66 so->lrz.enable = false;
67 so->lrz.test = false;
72 so->lrz.write = false;
79 so->lrz.write = false;
81 * effects from stencil test we need to disable lrz-test.
84 so->lrz.enable = false;
85 so->lrz.test = false
[all...] |
| fd6_zsa.h | 50 struct fd6_lrz_state lrz; member in struct:fd6_zsa_stateobj
|
| fd6_emit.c | 611 * Calculate normalized LRZ state based on zsa/prog/blend state, updating
612 * the zsbuf's lrz state as necessary to detect the cases where we need
613 * to invalidate lrz.
621 struct fd6_lrz_state lrz; variable in typeref:struct:fd6_lrz_state
624 memset(&lrz, 0, sizeof(lrz));
626 lrz.z_mode = compute_ztest_mode(emit, false);
628 return lrz;
635 lrz = zsa->lrz;
691 struct fd6_lrz_state lrz = compute_lrz_state(emit, binning_pass); variable in typeref:struct:fd6_lrz_state
[all...] |
| fd6_context.h | 92 /* previous binning/draw lrz state, which is a function of multiple
95 struct fd6_lrz_state lrz[2]; member in struct:fd6_context::__anon1197
|
| fd6_resource.c | 206 /* LRZ buffer is super-sampled: */
223 rsc->lrz = fd_bo_new(screen->dev, size, 0, "lrz");
|
| fd6_draw.c | 448 OUT_RELOC(ring, zsbuf->lrz, 0, 0, 0);
531 if (zsbuf->lrz && !is_z32(pfb->zsbuf->format)) {
|
| fd6_gmem.c | 172 if (rsc->lrz) {
173 OUT_REG(ring, A6XX_GRAS_LRZ_BUFFER_BASE(.bo = rsc->lrz),
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/a5xx/ |
| fd5_resource.c | 36 /* LRZ buffer is super-sampled: */
52 rsc->lrz = fd_bo_new(screen->dev, size, 0, "lrz");
60 if (FD_DBG(LRZ) && has_depth(rsc->b.b.format))
|
| fd5_draw.c | 124 /* figure out whether we need to disable LRZ write for binning
205 OUT_RING(ring, A5XX_RB_MRT_ARRAY_PITCH(fd_bo_size(zsbuf->lrz)));
206 OUT_RELOC(ring, zsbuf->lrz, 0x1000, 0, 0);
337 if (zsbuf->lrz) {
|
| fd5_gmem.c | 174 if (rsc->lrz) {
176 OUT_RELOC(ring, rsc->lrz, 0x1000, 0, 0);
180 OUT_RELOC(ring, rsc->lrz, 0, 0, 0);
|
| fd5_emit.c | 583 if (emit->no_lrz_write || !rsc->lrz || !rsc->lrz_valid)
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/freedreno/ |
| freedreno_resource.h | 108 * LRZ
111 uint16_t lrz_width; // for lrz clear, does this differ from lrz_pitch?
114 struct fd_bo *lrz; member in struct:fd_resource
|
| freedreno_resource.c | 946 // XXX probably need some extra work if we hit rsc shadowing path w/ lrz..
954 /* LRZ buffer is super-sampled: */
969 rsc->lrz = fd_bo_new(screen->dev, size, flags, "lrz");
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/freedreno/a5xx/ |
| fd5_draw.c | 142 /* figure out whether we need to disable LRZ write for binning
194 // splitting both clear and lrz clear out into their own rb's. And
231 OUT_RING(ring, A5XX_RB_MRT_ARRAY_PITCH(fd_bo_size(zsbuf->lrz)));
232 OUT_RELOCW(ring, zsbuf->lrz, 0x1000, 0, 0);
371 if (zsbuf->lrz) {
|
| fd5_gmem.c | 172 if (rsc->lrz) {
174 OUT_RELOCW(ring, rsc->lrz, 0x1000, 0, 0);
178 OUT_RELOCW(ring, rsc->lrz, 0, 0, 0);
|
| fd5_emit.c | 552 if (emit->no_lrz_write || !rsc->lrz || !rsc->lrz_valid)
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/freedreno/a6xx/ |
| fd6_draw.c | 202 /* figure out whether we need to disable LRZ write for binning
260 // splitting both clear and lrz clear out into their own rb's. And
329 OUT_RELOCW(ring, zsbuf->lrz, 0, 0, 0);
410 if (zsbuf->lrz && !is_z32(pfb->zsbuf->format)) {
|
| fd6_gmem.c | 200 if (rsc->lrz) {
202 OUT_RELOCW(ring, rsc->lrz, 0, 0, 0);
204 //OUT_RELOCW(ring, rsc->lrz, 0, 0, 0); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO/HI */
|
| fd6_emit.c | 699 if (emit->no_lrz_write || !rsc->lrz || !rsc->lrz_valid) {
|
| /xsrc/external/mit/MesaLib/dist/src/freedreno/vulkan/ |
| tu_cmd_buffer.c | 2996 /* After a secondary command buffer is executed, LRZ is not valid
2999 cmd->state.lrz.valid = false;
3180 /* Track LRZ valid state */
3185 /* if image has lrz and it isn't a stencil-only clear: */
3188 cmd->state.lrz.image = image;
3189 cmd->state.lrz.valid = true;
3190 cmd->state.lrz.prev_direction = TU_LRZ_UNKNOWN;
3194 /* Clearing writes via CCU color in the PS stage, and LRZ is read via
3201 cmd->state.lrz.valid = false;
3230 /* Track LRZ valid stat
[all...] |
| tu_private.h | 856 * GRAS reads and writes LRZ directly.
941 /* Depth/Stencil image currently on use to do LRZ */
1027 struct tu_lrz_state lrz; member in struct:tu_cmd_state
1263 struct tu_lrz_pipeline lrz; member in struct:tu_pipeline
|
| tu_pipeline.c | 1542 pipeline->lrz.fs_has_kill = fs->has_kill;
1543 pipeline->lrz.early_fragment_tests = fs->shader->nir->info.fs.early_fragment_tests;
1547 pipeline->lrz.force_late_z = true;
2963 pipeline->lrz.force_disable_mask |= TU_LRZ_FORCE_DISABLE_WRITE;
2966 pipeline->lrz.force_disable_mask = TU_LRZ_FORCE_DISABLE_LRZ;
3018 /* Disable LRZ writes when blend is enabled, since the
3020 * depends on an earlier draw, which LRZ in the draw pass
3021 * could early-reject if the previous blend-enabled draw wrote LRZ.
3023 * From the PoV of LRZ, having masked color channels is
3027 * TODO: We need to disable LRZ writes only for the binning pass
[all...] |
| tu_clear_blit.c | 2525 cmd->state.lrz.valid = false;
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/ |
| freedreno_resource.h | 159 * LRZ
161 * TODO lrz width/height/pitch should probably also move to
166 uint16_t lrz_width; // for lrz clear, does this differ from lrz_pitch?
169 struct fd_bo *lrz; member in struct:fd_resource
|
| freedreno_resource.c | 1006 if (rsc->lrz)
1007 fd_bo_del(rsc->lrz);
|
