| /xsrc/external/mit/MesaLib/dist/src/freedreno/ir3/ |
| H A D | ir3_delay.c | 95 /* In mergedregs mode, there is an extra 2-cycle penalty when half of
213 unsigned consumer_n, bool soft, bool mergedregs)
220 /* In the mergedregs case or when the register is a special register,
223 if ((!mergedregs || is_reg_special(src) || is_reg_special(dst)) &&
308 bool soft, bool pred, bool mergedregs)
337 assigner, consumer, dst_n, src_n, soft, mergedregs);
369 soft, pred, mergedregs);
388 * @mergedregs: True if mergedregs is enabled.
392 bool soft, bool mergedregs)
211 delay_calc_srcn_postra(struct ir3_instruction * assigner,struct ir3_instruction * consumer,unsigned assigner_n,unsigned consumer_n,bool soft,bool mergedregs) argument
306 delay_calc_postra(struct ir3_block * block,struct ir3_instruction * start,struct ir3_instruction * consumer,unsigned distance,bool soft,bool pred,bool mergedregs) argument
391 ir3_delay_calc_postra(struct ir3_block * block,struct ir3_instruction * instr,bool soft,bool mergedregs) argument
402 ir3_delay_calc_exact(struct ir3_block * block,struct ir3_instruction * instr,bool mergedregs) argument
[all...] |
| H A D | ir3_legalize.c | 97 bool mergedregs = ctx->so->mergedregs; local in function:legalize_block
156 regmask_init(&state->needs_ss_war, mergedregs);
157 regmask_init(&state->needs_ss, mergedregs);
158 regmask_init(&state->needs_sy, mergedregs);
163 regmask_init(&state->needs_ss_war, mergedregs);
164 regmask_init(&state->needs_ss, mergedregs);
189 regmask_init(&state->needs_ss_war, mergedregs);
190 regmask_init(&state->needs_ss, mergedregs);
195 regmask_init(&state->needs_sy, mergedregs);
845 bool mergedregs = so->mergedregs; local in function:ir3_legalize
[all...] |
| H A D | ir3_postsched.c | 219 ir3_delay_calc_postra(ctx->block, n->instr, false, ctx->v->mergedregs);
239 ir3_delay_calc_postra(ctx->block, n->instr, false, ctx->v->mergedregs);
270 ctx->v->mergedregs);
292 ir3_delay_calc_postra(ctx->block, n->instr, true, ctx->v->mergedregs);
312 ir3_delay_calc_postra(ctx->block, n->instr, false, ctx->v->mergedregs);
496 .merged = ctx->v->mergedregs,
510 .merged = ctx->v->mergedregs,
681 ir3_delay_calc_postra(ctx->block, instr, false, ctx->v->mergedregs);
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| H A D | ir3.h | 1626 bool mergedregs);
1628 struct ir3_instruction *instr, bool mergedregs);
2218 bool mergedregs; member in struct:__anon3fdcb7e61308
2225 if (regmask->mergedregs) {
2253 if (regmask->mergedregs) {
2278 if (regmask->mergedregs) {
2301 regmask_init(regmask_t *regmask, bool mergedregs) argument
2304 regmask->mergedregs = mergedregs;
2310 assert(dst->mergedregs
[all...] |
| H A D | ir3_shader.c | 84 if (!v->mergedregs) {
101 if (!v->mergedregs) {
115 if (!v->mergedregs) {
335 v->mergedregs = shader->compiler->gen >= 6;
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| H A D | ir3_ra.c | 119 * in mergedregs mode, and count as 4 half-units of register pressure
2118 add_pressure(&cur_pressure, input->dsts[0], v->mergedregs);
2135 if (!(dst->flags & IR3_REG_HALF) || v->mergedregs)
2169 add_pressure(&cur_pressure, dst, v->mergedregs);
2183 add_pressure(&cur_pressure, interval->reg, v->mergedregs);
2197 add_pressure(&cur_pressure, dst, v->mergedregs);
2220 ctx->merged_regs = v->mergedregs;
2276 if (!v->mergedregs)
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| H A D | ir3_shader.h | 661 bool mergedregs; member in struct:ir3_shader_variant
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| H A D | ir3_lower_parallelcopy.c | 363 * mergedregs case, we can 32-bit copies which are only blocked on one
487 if (v->mergedregs) {
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| H A D | ir3_ra_validate.c | 556 ctx->merged_regs = v->mergedregs;
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| H A D | ir3.c | 101 if (v->mergedregs) {
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| H A D | ir3_spill.c | 458 ctx->merged_regs = v->mergedregs;
|
| /xsrc/external/mit/MesaLib/dist/src/freedreno/computerator/ |
| H A D | ir3_asm.c | 38 v->mergedregs = true;
|
| H A D | a6xx.c | 155 COND(v->mergedregs, A6XX_SP_CS_CTRL_REG0_MERGEDREGS) |
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/a6xx/ |
| H A D | fd6_program.c | 527 COND(vs->mergedregs, A6XX_SP_VS_CTRL_REG0_MERGEDREGS) |
650 assert(vs->mergedregs == hs->mergedregs);
667 COND(ds->mergedregs, A6XX_SP_DS_CTRL_REG0_MERGEDREGS) |
825 COND(fs->mergedregs, A6XX_SP_FS_CTRL_REG0_MERGEDREGS) |
918 assert(gs->mergedregs == (ds ? ds->mergedregs : vs->mergedregs));
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| H A D | fd6_compute.c | 70 COND(v->mergedregs, A6XX_SP_CS_CTRL_REG0_MERGEDREGS) |
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| /xsrc/external/mit/MesaLib/dist/docs/relnotes/ |
| H A D | 20.2.3.rst | 76 - freedreno/cffdec: When .mergedregs is set, don't count half regs.
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| H A D | 20.2.0.rst | 4106 - freedreno/ir3: make mergedregs a property of the variant
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| H A D | 20.3.0.rst | 1453 - freedreno/cffdec: When .mergedregs is set, don't count half regs.
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| /xsrc/external/mit/MesaLib/dist/src/freedreno/vulkan/ |
| H A D | tu_pipeline.c | 474 .mergedregs = xs->mergedregs,
489 .mergedregs = xs->mergedregs,
504 .mergedregs = xs->mergedregs,
518 .mergedregs = xs->mergedregs,
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| /xsrc/external/mit/MesaLib/dist/ |
| H A D | .pick_status.json | [all...] |