Searched refs:meta_offset (Results 1 - 20 of 20) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/amd/common/
H A Dac_surface_modifier_test.c126 _mesa_sha1_update(&ctx, &surf->meta_offset, sizeof(surf->meta_offset));
145 if (surf->meta_offset) {
175 if (surf->meta_offset) {
318 assert(surf.meta_offset == expected_offset);
328 assert(!surf.meta_offset);
H A Dac_surface.c2403 surf->meta_offset = surf->display_dcc_offset = surf->fmask_offset = surf->cmask_offset = 0;
2436 surf->meta_offset = align64(surf->total_size, 1 << surf->meta_alignment_log2);
2437 surf->total_size = surf->meta_offset + surf->meta_size;
2450 surf->meta_offset = 0;
2560 if (surf->meta_offset) {
2561 dcc_offset = surf->display_dcc_offset ? surf->display_dcc_offset : surf->meta_offset;
2661 surf->meta_offset = (uint64_t)desc[7] << 8;
2665 surf->meta_offset =
2677 surf->meta_offset =
2709 desc[7] = surf->meta_offset >>
[all...]
H A Dac_surface.h378 uint64_t meta_offset; /* DCC or HTILE */ member in struct:radeon_surf
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_compute_blit.c604 assert(tex->surface.meta_offset && tex->surface.meta_offset <= UINT_MAX);
606 assert(tex->surface.display_dcc_offset < tex->surface.meta_offset);
614 sctx->cs_user_data[0] = tex->surface.meta_offset - tex->surface.display_dcc_offset;
653 assert(tex->surface.meta_offset && tex->surface.meta_offset <= UINT_MAX);
658 sb.buffer_offset = tex->surface.meta_offset;
H A Dsi_texture.c352 tex->surface.meta_offset &&
486 tex->surface.meta_offset = new_tex->surface.meta_offset;
507 assert(!tex->surface.meta_offset);
556 return tex->surface.is_displayable && tex->surface.meta_offset;
703 if ((usage & PIPE_HANDLE_USAGE_SHADER_WRITE && !tex->is_depth && tex->surface.meta_offset) ||
715 (tex->cmask_buffer || (!tex->is_depth && tex->surface.meta_offset))) {
815 if (tex->is_depth && tex->surface.meta_offset)
833 if (!tex->is_depth && tex->surface.meta_offset) {
1031 if (tex->is_depth && tex->surface.meta_offset) {
[all...]
H A Dsi_clear.c297 uint64_t dcc_offset = tex->surface.meta_offset;
836 zstex->surface.meta_offset, zstex->surface.meta_size, clear_value);
847 uint64_t htile_offset = zstex->surface.meta_offset;
H A Dsi_pipe.h1611 return !tex->is_depth && tex->surface.meta_offset && level < tex->surface.num_meta_levels;
1797 if (!tex->is_depth || !tex->surface.meta_offset)
1815 assert(!tex->tc_compatible_htile || tex->surface.meta_offset);
H A Dsi_sdma_copy_image.c202 uint64_t md_address = tiled_address + tiled->surface.meta_offset;
H A Dsi_descriptors.c323 meta_va = tex->buffer.gpu_address + tex->surface.meta_offset;
335 meta_va = tex->buffer.gpu_address + tex->surface.meta_offset;
358 if (!tex->is_depth && tex->surface.meta_offset)
404 if (!tex->is_depth && tex->surface.meta_offset)
490 (tex->dirty_level_mask && (tex->cmask_buffer || tex->surface.meta_offset));
H A Dsi_blit.c1365 if (!tex->surface.meta_offset || !sctx->has_graphics)
1396 si_clear_buffer(sctx, ptex, tex->surface.meta_offset,
H A Dsi_state.c2591 surf->db_htile_data_base = (tex->buffer.gpu_address + tex->surface.meta_offset) >> 8;
2663 surf->db_htile_data_base = (tex->buffer.gpu_address + tex->surface.meta_offset) >> 8;
3114 cb_dcc_base = (tex->buffer.gpu_address + tex->surface.meta_offset) >> 8;
3168 if (!tex->is_depth && tex->surface.meta_offset)
/xsrc/external/mit/MesaLib/dist/src/gallium/winsys/radeon/drm/
H A Dradeon_drm_surface.c442 surf_ws->meta_offset = align64(surf_ws->total_size, 1 << surf_ws->meta_alignment_log2);
443 surf_ws->total_size = surf_ws->meta_offset + surf_ws->meta_size;
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_meta_dcc_retile.c225 .offset = image->planes[0].surface.meta_offset,
H A Dradv_image.c752 meta_va = gpu_address + plane->surface.meta_offset;
760 meta_va = gpu_address + plane->surface.meta_offset;
1112 image->planes[0].surface.meta_offset) {
1270 (surface->display_dcc_offset ? surface->display_dcc_offset : surface->meta_offset);
H A Dradv_meta_clear.c1470 uint64_t offset = image->offset + image->planes[0].surface.meta_offset;
1637 uint64_t offset = image->offset + image->planes[0].surface.meta_offset +
1657 uint64_t offset = image->offset + image->planes[0].surface.meta_offset +
H A Dradv_device.c6625 if (surf->meta_offset)
6676 va += surf->meta_offset;
6974 va = radv_buffer_get_va(iview->image->bo) + iview->image->offset + surf->meta_offset;
7043 va = radv_buffer_get_va(iview->image->bo) + iview->image->offset + surf->meta_offset;
H A Dradv_private.h2038 image->planes[0].surface.meta_offset;
H A Dradv_cmd_buffer.c5770 uint64_t htile_offset = ds_image->offset + ds_image->planes[0].surface.meta_offset;
7445 image->offset + image->planes[0].surface.meta_offset + size,
7533 image->planes[0].surface.display_dcc_offset != image->planes[0].surface.meta_offset;
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeon/
H A Dradeon_vcn_enc_1_2.c1150 if (enc->luma->meta_offset) {
1200 if (enc->luma->meta_offset) {
H A Dradeon_vcn_dec.c1667 if (luma->surface.meta_offset) {

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