| /xsrc/external/mit/MesaLib.old/dist/src/gallium/winsys/radeon/drm/ |
| radeon_drm_surface.c | 153 surf_drm->mtilea = surf_ws->u.legacy.mtilea;
195 surf_ws->u.legacy.mtilea = surf_drm->mtilea;
|
| /xsrc/external/mit/libdrm/dist/radeon/ |
| radeon_surface.h | 132 uint32_t mtilea; member in struct:radeon_surface
|
| radeon_surface.c | 675 mtilew = (tilew * surf->bankw * surf_man->hw_info.num_pipes) * surf->mtilea;
676 mtileh = (tileh * surf->bankh * surf_man->hw_info.num_banks) / surf->mtilea;
746 switch (surf->mtilea) {
756 if (surf_man->hw_info.num_banks < surf->mtilea) {
905 /* compute best tile_split, bankw, bankh, mtilea
921 surf->mtilea = surf_man->hw_info.num_banks;
928 if (surf->mtilea > 8) {
929 surf->mtilea = 8;
1020 surf->mtilea = 1 << (log2_int(h_over_w) >> 1);
1320 surf->mtilea = 1
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/ |
| radeon_video.c | 179 surfaces[i]->u.legacy.mtilea = surfaces[best_tiling]->u.legacy.mtilea;
|
| r600_texture.c | 287 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
303 surf->u.legacy.mtilea = metadata->u.legacy.mtilea;
611 fmask.u.legacy.mtilea = rtex->surface.u.legacy.mtilea;
839 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
841 rtex->surface.u.legacy.bankh, rtex->surface.u.legacy.num_banks, rtex->surface.u.legacy.mtilea,
|
| radeon_uvd.c | 1243 assert(luma->u.legacy.mtilea == chroma->u.legacy.mtilea);
1248 msg->body.decode.dt_surf_tile_config |= RUVD_MACRO_TILE_ASPECT_RATIO(macro_tile_aspect(luma->u.legacy.mtilea));
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/ |
| radeon_video.c | 179 surfaces[i]->u.legacy.mtilea = surfaces[best_tiling]->u.legacy.mtilea;
|
| r600_texture.c | 288 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
304 surf->u.legacy.mtilea = metadata->u.legacy.mtilea;
616 fmask.u.legacy.mtilea = rtex->surface.u.legacy.mtilea;
844 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
846 rtex->surface.u.legacy.bankh, rtex->surface.u.legacy.num_banks, rtex->surface.u.legacy.mtilea,
|
| radeon_uvd.c | 1487 assert(luma->u.legacy.mtilea == chroma->u.legacy.mtilea);
1492 msg->body.decode.dt_surf_tile_config |= RUVD_MACRO_TILE_ASPECT_RATIO(macro_tile_aspect(luma->u.legacy.mtilea));
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeon/ |
| radeon_video.c | 170 surfaces[i]->u.legacy.mtilea = surfaces[best_tiling]->u.legacy.mtilea;
|
| radeon_winsys.h | 212 unsigned mtilea; member in struct:radeon_bo_metadata::__anon4022::__anon4023
|
| radeon_uvd.c | 1465 assert(luma->u.legacy.mtilea == chroma->u.legacy.mtilea);
1470 msg->body.decode.dt_surf_tile_config |= RUVD_MACRO_TILE_ASPECT_RATIO(macro_tile_aspect(luma->u.legacy.mtilea));
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/winsys/radeon/drm/ |
| radeon_drm_surface.c | 153 surf_drm->mtilea = surf_ws->u.legacy.mtilea;
195 surf_ws->u.legacy.mtilea = surf_drm->mtilea;
|
| radeon_drm_bo.c | 908 surf->u.legacy.mtilea = (args.tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
930 md->u.legacy.mtilea = (args.tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
964 args.tiling_flags |= (surf->u.legacy.mtilea & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK) <<
989 args.tiling_flags |= (md->u.legacy.mtilea & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK) <<
|
| /xsrc/external/mit/MesaLib.old/dist/src/amd/common/ |
| ac_surface.h | 97 unsigned mtilea:4; /* max 8 */ member in struct:legacy_surf_layout
|
| ac_surface.c | 520 surf->u.legacy.mtilea = csio->pTileInfo->macroAspectRatio;
779 surf->u.legacy.mtilea && surf->u.legacy.tile_split) {
785 AddrTileInfoIn.macroAspectRatio = surf->u.legacy.mtilea;
|
| /xsrc/external/mit/xf86-video-ati-kms/dist/src/ |
| radeon_bo_helper.c | 165 surface->mtilea = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) &
283 tiling |= surface.mtilea << RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT;
|
| /xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/ |
| radv_radeon_winsys.h | 145 unsigned mtilea; member in struct:radeon_bo_metadata::__anon3266::__anon3267
|
| /xsrc/external/mit/MesaLib/dist/src/amd/common/ |
| ac_surface.h | 116 unsigned mtilea : 4; /* max 8 */ member in struct:legacy_surf_layout
|
| /xsrc/external/mit/MesaLib/dist/src/amd/vulkan/ |
| radv_radeon_winsys.h | 137 unsigned mtilea; member in struct:radeon_bo_metadata::__anon582::__anon583
|
| radv_image.c | 437 surface->u.legacy.mtilea = md->u.legacy.mtilea;
1290 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeon/ |
| radeon_winsys.h | 231 unsigned mtilea; member in struct:radeon_bo_metadata::__anon1579::__anon1580
|
| radeon_uvd.c | 1476 assert(luma->u.legacy.mtilea == chroma->u.legacy.mtilea);
1482 RUVD_MACRO_TILE_ASPECT_RATIO(macro_tile_aspect(luma->u.legacy.mtilea));
|
| /xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/winsys/amdgpu/ |
| radv_amdgpu_bo.c | 676 tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT, util_logbase2(md->u.legacy.mtilea));
720 md->u.legacy.mtilea = 1 << AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
|
| /xsrc/external/mit/MesaLib/dist/src/amd/vulkan/winsys/amdgpu/ |
| radv_amdgpu_bo.c | 939 tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT, util_logbase2(md->u.legacy.mtilea));
985 md->u.legacy.mtilea = 1 << AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
|
