Searched refs:mtilea (Results 1 - 25 of 37) sorted by relevance

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/xsrc/external/mit/libdrm/dist/radeon/
H A Dradeon_surface.h132 uint32_t mtilea; member in struct:radeon_surface
H A Dradeon_surface.c675 mtilew = (tilew * surf->bankw * surf_man->hw_info.num_pipes) * surf->mtilea;
676 mtileh = (tileh * surf->bankh * surf_man->hw_info.num_banks) / surf->mtilea;
746 switch (surf->mtilea) {
756 if (surf_man->hw_info.num_banks < surf->mtilea) {
905 /* compute best tile_split, bankw, bankh, mtilea
921 surf->mtilea = surf_man->hw_info.num_banks;
928 if (surf->mtilea > 8) {
929 surf->mtilea = 8;
1020 surf->mtilea = 1 << (log2_int(h_over_w) >> 1);
1320 surf->mtilea
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/gallium/winsys/radeon/drm/
H A Dradeon_drm_surface.c153 surf_drm->mtilea = surf_ws->u.legacy.mtilea;
195 surf_ws->u.legacy.mtilea = surf_drm->mtilea;
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/
H A Dradeon_video.c179 surfaces[i]->u.legacy.mtilea = surfaces[best_tiling]->u.legacy.mtilea;
H A Dr600_texture.c288 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
304 surf->u.legacy.mtilea = metadata->u.legacy.mtilea;
616 fmask.u.legacy.mtilea = rtex->surface.u.legacy.mtilea;
844 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
846 rtex->surface.u.legacy.bankh, rtex->surface.u.legacy.num_banks, rtex->surface.u.legacy.mtilea,
H A Dradeon_uvd.c1487 assert(luma->u.legacy.mtilea == chroma->u.legacy.mtilea);
1492 msg->body.decode.dt_surf_tile_config |= RUVD_MACRO_TILE_ASPECT_RATIO(macro_tile_aspect(luma->u.legacy.mtilea));
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeon/
H A Dradeon_video.c170 surfaces[i]->u.legacy.mtilea = surfaces[best_tiling]->u.legacy.mtilea;
H A Dradeon_winsys.h212 unsigned mtilea; member in struct:radeon_bo_metadata::__anonaf1fea34010a::__anonaf1fea340208
H A Dradeon_uvd.c1465 assert(luma->u.legacy.mtilea == chroma->u.legacy.mtilea);
1470 msg->body.decode.dt_surf_tile_config |= RUVD_MACRO_TILE_ASPECT_RATIO(macro_tile_aspect(luma->u.legacy.mtilea));
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/
H A Dradeon_video.c179 surfaces[i]->u.legacy.mtilea = surfaces[best_tiling]->u.legacy.mtilea;
H A Dr600_texture.c287 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
303 surf->u.legacy.mtilea = metadata->u.legacy.mtilea;
611 fmask.u.legacy.mtilea = rtex->surface.u.legacy.mtilea;
839 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
841 rtex->surface.u.legacy.bankh, rtex->surface.u.legacy.num_banks, rtex->surface.u.legacy.mtilea,
H A Dradeon_uvd.c1243 assert(luma->u.legacy.mtilea == chroma->u.legacy.mtilea);
1248 msg->body.decode.dt_surf_tile_config |= RUVD_MACRO_TILE_ASPECT_RATIO(macro_tile_aspect(luma->u.legacy.mtilea));
/xsrc/external/mit/MesaLib.old/dist/src/amd/common/
H A Dac_surface.h97 unsigned mtilea:4; /* max 8 */ member in struct:legacy_surf_layout
H A Dac_surface.c520 surf->u.legacy.mtilea = csio->pTileInfo->macroAspectRatio;
779 surf->u.legacy.mtilea && surf->u.legacy.tile_split) {
785 AddrTileInfoIn.macroAspectRatio = surf->u.legacy.mtilea;
/xsrc/external/mit/MesaLib/dist/src/gallium/winsys/radeon/drm/
H A Dradeon_drm_surface.c153 surf_drm->mtilea = surf_ws->u.legacy.mtilea;
195 surf_ws->u.legacy.mtilea = surf_drm->mtilea;
H A Dradeon_drm_bo.c908 surf->u.legacy.mtilea = (args.tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
930 md->u.legacy.mtilea = (args.tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
964 args.tiling_flags |= (surf->u.legacy.mtilea & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK) <<
989 args.tiling_flags |= (md->u.legacy.mtilea & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK) <<
/xsrc/external/mit/xf86-video-ati-kms/dist/src/
H A Dradeon_bo_helper.c165 surface->mtilea = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) &
283 tiling |= surface.mtilea << RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT;
/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
H A Dradv_radeon_winsys.h145 unsigned mtilea; member in struct:radeon_bo_metadata::__anon996f74f1010a::__anon996f74f10208
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_radeon_winsys.h137 unsigned mtilea; member in struct:radeon_bo_metadata::__anonc88d74e4010a::__anonc88d74e40208
H A Dradv_image.c437 surface->u.legacy.mtilea = md->u.legacy.mtilea;
1290 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
/xsrc/external/mit/MesaLib/dist/src/amd/common/
H A Dac_surface.h116 unsigned mtilea : 4; /* max 8 */ member in struct:legacy_surf_layout
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeon/
H A Dradeon_winsys.h231 unsigned mtilea; member in struct:radeon_bo_metadata::__anonf1261ac7010a::__anonf1261ac70208
H A Dradeon_uvd.c1476 assert(luma->u.legacy.mtilea == chroma->u.legacy.mtilea);
1482 RUVD_MACRO_TILE_ASPECT_RATIO(macro_tile_aspect(luma->u.legacy.mtilea));
/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/winsys/amdgpu/
H A Dradv_amdgpu_bo.c676 tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT, util_logbase2(md->u.legacy.mtilea));
720 md->u.legacy.mtilea = 1 << AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
/xsrc/external/mit/xf86-video-ati/dist/src/
H A Devergreen_accel.c230 macro_aspect = cb_conf->surface->mtilea;
716 macro_aspect = tex_res->surface->mtilea;

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