HomeSort by: relevance | last modified time | path
    Searched refs:num_banks (Results 1 - 25 of 31) sorted by relevancy

1 2

  /xsrc/external/mit/MesaLib/dist/src/amd/addrlib/src/chip/r800/
si_gb_reg.h 112 unsigned int num_banks : 2; member in struct:_GB_TILE_MODE_T
122 unsigned int num_banks : 2; member in struct:_GB_MACROTILE_MODE_T
135 unsigned int num_banks : 2; member in struct:_GB_TILE_MODE_T
150 unsigned int num_banks : 2; member in struct:_GB_MACROTILE_MODE_T
  /xsrc/external/mit/MesaLib.old/dist/src/amd/addrlib/src/chip/r800/
si_gb_reg.h 112 unsigned int num_banks : 2; member in struct:_GB_TILE_MODE_T
122 unsigned int num_banks : 2; member in struct:_GB_MACROTILE_MODE_T
132 unsigned int num_banks : 2; member in struct:_GB_TILE_MODE_T
144 unsigned int num_banks : 2; member in struct:_GB_MACROTILE_MODE_T
  /xsrc/external/mit/libdrm/dist/radeon/
radeon_surface.c 103 uint32_t num_banks; member in struct:radeon_hw_info
240 surf_man->hw_info.num_banks = 4;
243 surf_man->hw_info.num_banks = 8;
246 surf_man->hw_info.num_banks = 8;
371 xalign = (surf_man->hw_info.group_bytes * surf_man->hw_info.num_banks) /
373 xalign = MAX2(tilew * surf_man->hw_info.num_banks, xalign);
383 surf_man->hw_info.num_banks *
525 surf_man->hw_info.num_banks = 4;
528 surf_man->hw_info.num_banks = 8;
531 surf_man->hw_info.num_banks = 16
1705 unsigned num_pipes, num_banks; local
2309 uint32_t num_pipes, num_banks; local
    [all...]
  /xsrc/external/mit/MesaLib.old/dist/src/amd/common/
ac_surface.h 101 unsigned num_banks:5; /* max 16 */ member in struct:legacy_surf_layout
ac_surface.c 522 surf->u.legacy.num_banks = csio->pTileInfo->banks;
782 AddrTileInfoIn.banks = surf->u.legacy.num_banks;
  /xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
radv_radeon_winsys.h 146 unsigned num_banks; member in struct:radeon_bo_metadata::__anon3266::__anon3267
radv_image.c 757 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
  /xsrc/external/mit/xf86-video-ati/dist/src/
radeon_kms.c 540 info->num_banks = 4;
543 info->num_banks = 8;
546 info->num_banks = 16;
583 info->num_banks = 4;
586 info->num_banks = 8;
drmmode_display.c 1193 pitch_align = MAX(info->num_banks,
1194 (((info->group_bytes / 8) / bpe) * info->num_banks)) * 8;
1196 pitch_align = MAX(info->num_banks * 8, pitch_align);
1234 base_align = MAX(info->num_banks * info->num_channels * 8 * 8 * bpe,
evergreen_accel.c 250 nbanks = info->num_banks;
733 nbanks = info->num_banks;
  /xsrc/external/mit/MesaLib/dist/src/amd/common/
ac_surface.h 120 unsigned num_banks : 5; /* max 16 */ member in struct:legacy_surf_layout
ac_surface.c 856 surf->u.legacy.num_banks = csio->pTileInfo->banks;
1113 AddrTileInfoIn.banks = surf->u.legacy.num_banks;
2535 surf->u.legacy.num_banks = 2 << AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2590 *tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, util_logbase2(surf->u.legacy.num_banks) - 1);
2976 surf->u.legacy.num_banks, surf->u.legacy.mtilea,
  /xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
radv_radeon_winsys.h 138 unsigned num_banks; member in struct:radeon_bo_metadata::__anon582::__anon583
radv_image.c 438 surface->u.legacy.num_banks = md->u.legacy.num_banks;
1291 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeon/
radeon_winsys.h 213 unsigned num_banks; member in struct:radeon_bo_metadata::__anon4022::__anon4023
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeon/
radeon_winsys.h 232 unsigned num_banks; member in struct:radeon_bo_metadata::__anon1579::__anon1580
  /xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/winsys/amdgpu/
radv_amdgpu_bo.c 677 tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, util_logbase2(md->u.legacy.num_banks)-1);
721 md->u.legacy.num_banks = 2 << AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/
r600_texture.c 288 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
304 surf->u.legacy.num_banks = metadata->u.legacy.num_banks;
841 rtex->surface.u.legacy.bankh, rtex->surface.u.legacy.num_banks, rtex->surface.u.legacy.mtilea,
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/
r600_texture.c 289 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
305 surf->u.legacy.num_banks = metadata->u.legacy.num_banks;
846 rtex->surface.u.legacy.bankh, rtex->surface.u.legacy.num_banks, rtex->surface.u.legacy.mtilea,
  /xsrc/external/mit/xf86-video-ati-kms/dist/src/
radeon_kms.c 1620 info->num_banks = 4;
1623 info->num_banks = 8;
1626 info->num_banks = 16;
1663 info->num_banks = 4;
1666 info->num_banks = 8;
evergreen_accel.c 244 nbanks = info->num_banks;
722 nbanks = info->num_banks;
drmmode_display.c 2354 pitch_align = MAX(info->num_banks,
2355 (((info->group_bytes / 8) / bpe) * info->num_banks)) * 8;
2357 pitch_align = MAX(info->num_banks * 8, pitch_align);
2395 base_align = MAX(info->num_banks * info->num_channels * 8 * 8 * bpe,
  /xsrc/external/mit/MesaLib/dist/src/amd/vulkan/winsys/amdgpu/
radv_amdgpu_bo.c 940 tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, util_logbase2(md->u.legacy.num_banks) - 1);
986 md->u.legacy.num_banks = 2 << AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
si_texture.c 366 surf->u.legacy.num_banks = metadata->u.legacy.num_banks;
651 md.u.legacy.num_banks = surface->u.legacy.num_banks;
1125 tex->surface.u.legacy.bankh, tex->surface.u.legacy.num_banks, tex->surface.u.legacy.mtilea,
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/winsys/amdgpu/drm/
amdgpu_bo.c 1249 md->u.legacy.num_banks = 2 << AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1286 tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, util_logbase2(md->u.legacy.num_banks)-1);

Completed in 48 milliseconds

1 2