Searched refs:num_banks (Results 1 - 25 of 31) sorted by relevance

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/xsrc/external/mit/MesaLib.old/dist/src/amd/addrlib/src/chip/r800/
H A Dsi_gb_reg.h112 unsigned int num_banks : 2; member in struct:_GB_TILE_MODE_T
122 unsigned int num_banks : 2; member in struct:_GB_MACROTILE_MODE_T
132 unsigned int num_banks : 2; member in struct:_GB_TILE_MODE_T
144 unsigned int num_banks : 2; member in struct:_GB_MACROTILE_MODE_T
/xsrc/external/mit/MesaLib/dist/src/amd/addrlib/src/chip/r800/
H A Dsi_gb_reg.h112 unsigned int num_banks : 2; member in struct:_GB_TILE_MODE_T
122 unsigned int num_banks : 2; member in struct:_GB_MACROTILE_MODE_T
135 unsigned int num_banks : 2; member in struct:_GB_TILE_MODE_T
150 unsigned int num_banks : 2; member in struct:_GB_MACROTILE_MODE_T
/xsrc/external/mit/libdrm/dist/radeon/
H A Dradeon_surface.c103 uint32_t num_banks; member in struct:radeon_hw_info
240 surf_man->hw_info.num_banks = 4;
243 surf_man->hw_info.num_banks = 8;
246 surf_man->hw_info.num_banks = 8;
371 xalign = (surf_man->hw_info.group_bytes * surf_man->hw_info.num_banks) /
373 xalign = MAX2(tilew * surf_man->hw_info.num_banks, xalign);
383 surf_man->hw_info.num_banks *
525 surf_man->hw_info.num_banks = 4;
528 surf_man->hw_info.num_banks = 8;
531 surf_man->hw_info.num_banks
1072 si_gb_tile_mode(uint32_t gb_tile_mode,unsigned * num_pipes,unsigned * num_banks,uint32_t * macro_tile_aspect,uint32_t * bank_w,uint32_t * bank_h,uint32_t * tile_split) argument
1617 si_surface_init_2d(struct radeon_surface_manager * surf_man,struct radeon_surface * surf,struct radeon_surface_level * level,unsigned bpe,unsigned tile_mode,unsigned num_pipes,unsigned num_banks,unsigned tile_split,uint64_t offset,unsigned start_level) argument
1705 unsigned num_pipes, num_banks; local in function:si_surface_init_2d_miptrees
1857 cik_get_2d_params(struct radeon_surface_manager * surf_man,unsigned bpe,unsigned nsamples,bool is_color,unsigned tile_mode,uint32_t * num_pipes,uint32_t * tile_split_ptr,uint32_t * num_banks,uint32_t * macro_tile_aspect,uint32_t * bank_w,uint32_t * bank_h) argument
2215 cik_surface_init_2d(struct radeon_surface_manager * surf_man,struct radeon_surface * surf,struct radeon_surface_level * level,unsigned bpe,unsigned tile_mode,unsigned tile_split,unsigned num_pipes,unsigned num_banks,uint64_t offset,unsigned start_level) argument
2309 uint32_t num_pipes, num_banks; local in function:cik_surface_init_2d_miptrees
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/xsrc/external/mit/MesaLib.old/dist/src/amd/common/
H A Dac_surface.h101 unsigned num_banks:5; /* max 16 */ member in struct:legacy_surf_layout
H A Dac_surface.c522 surf->u.legacy.num_banks = csio->pTileInfo->banks;
782 AddrTileInfoIn.banks = surf->u.legacy.num_banks;
/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
H A Dradv_radeon_winsys.h146 unsigned num_banks; member in struct:radeon_bo_metadata::__anon996f74f1010a::__anon996f74f10208
H A Dradv_image.c757 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
/xsrc/external/mit/xf86-video-ati/dist/src/
H A Dradeon_kms.c540 info->num_banks = 4;
543 info->num_banks = 8;
546 info->num_banks = 16;
583 info->num_banks = 4;
586 info->num_banks = 8;
H A Ddrmmode_display.c1193 pitch_align = MAX(info->num_banks,
1194 (((info->group_bytes / 8) / bpe) * info->num_banks)) * 8;
1196 pitch_align = MAX(info->num_banks * 8, pitch_align);
1234 base_align = MAX(info->num_banks * info->num_channels * 8 * 8 * bpe,
H A Devergreen_accel.c250 nbanks = info->num_banks;
733 nbanks = info->num_banks;
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_radeon_winsys.h138 unsigned num_banks; member in struct:radeon_bo_metadata::__anonc88d74e4010a::__anonc88d74e40208
H A Dradv_image.c438 surface->u.legacy.num_banks = md->u.legacy.num_banks;
1291 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeon/
H A Dradeon_winsys.h213 unsigned num_banks; member in struct:radeon_bo_metadata::__anonaf1fea34010a::__anonaf1fea340208
/xsrc/external/mit/MesaLib/dist/src/amd/common/
H A Dac_surface.h120 unsigned num_banks : 5; /* max 16 */ member in struct:legacy_surf_layout
H A Dac_surface.c856 surf->u.legacy.num_banks = csio->pTileInfo->banks;
1113 AddrTileInfoIn.banks = surf->u.legacy.num_banks;
2535 surf->u.legacy.num_banks = 2 << AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2590 *tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, util_logbase2(surf->u.legacy.num_banks) - 1);
2976 surf->u.legacy.num_banks, surf->u.legacy.mtilea,
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeon/
H A Dradeon_winsys.h232 unsigned num_banks; member in struct:radeon_bo_metadata::__anonf1261ac7010a::__anonf1261ac70208
/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/winsys/amdgpu/
H A Dradv_amdgpu_bo.c677 tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, util_logbase2(md->u.legacy.num_banks)-1);
721 md->u.legacy.num_banks = 2 << AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
/xsrc/external/mit/xf86-video-ati-kms/dist/src/
H A Dradeon_kms.c1620 info->num_banks = 4;
1623 info->num_banks = 8;
1626 info->num_banks = 16;
1663 info->num_banks = 4;
1666 info->num_banks = 8;
H A Devergreen_accel.c244 nbanks = info->num_banks;
722 nbanks = info->num_banks;
H A Ddrmmode_display.c2354 pitch_align = MAX(info->num_banks,
2355 (((info->group_bytes / 8) / bpe) * info->num_banks)) * 8;
2357 pitch_align = MAX(info->num_banks * 8, pitch_align);
2395 base_align = MAX(info->num_banks * info->num_channels * 8 * 8 * bpe,
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/
H A Dr600_texture.c289 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
305 surf->u.legacy.num_banks = metadata->u.legacy.num_banks;
846 rtex->surface.u.legacy.bankh, rtex->surface.u.legacy.num_banks, rtex->surface.u.legacy.mtilea,
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/
H A Dr600_texture.c288 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
304 surf->u.legacy.num_banks = metadata->u.legacy.num_banks;
841 rtex->surface.u.legacy.bankh, rtex->surface.u.legacy.num_banks, rtex->surface.u.legacy.mtilea,
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/winsys/amdgpu/
H A Dradv_amdgpu_bo.c940 tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, util_logbase2(md->u.legacy.num_banks) - 1);
986 md->u.legacy.num_banks = 2 << AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_texture.c366 surf->u.legacy.num_banks = metadata->u.legacy.num_banks;
651 md.u.legacy.num_banks = surface->u.legacy.num_banks;
1125 tex->surface.u.legacy.bankh, tex->surface.u.legacy.num_banks, tex->surface.u.legacy.mtilea,
/xsrc/external/mit/MesaLib.old/dist/src/gallium/winsys/amdgpu/drm/
H A Damdgpu_bo.c1249 md->u.legacy.num_banks = 2 << AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1286 tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, util_logbase2(md->u.legacy.num_banks)-1);

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