Searched refs:offset_256B (Results 1 - 21 of 21) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeon/
H A Dradeon_vce_50.c121 (uint64_t)enc->luma->u.legacy.level[0].offset_256B * 256); // inputPictureLumaAddressHi/Lo
123 (uint64_t)enc->chroma->u.legacy.level[0].offset_256B * 256); // inputPictureChromaAddressHi/Lo
H A Dradeon_vce_40_2_2.c311 (uint64_t)enc->luma->u.legacy.level[0].offset_256B * 256); // inputPictureLumaAddressHi/Lo
313 (uint64_t)enc->chroma->u.legacy.level[0].offset_256B * 256); // inputPictureChromaAddressHi/Lo
H A Dradeon_uvd_enc_1_1.c901 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, (uint64_t)enc->luma->u.legacy.level[0].offset_256B * 256);
902 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, (uint64_t)enc->chroma->u.legacy.level[0].offset_256B * 256);
H A Dradeon_vce_52.c266 (uint64_t)enc->luma->u.legacy.level[0].offset_256B * 256); // inputPictureLumaAddressHi/Lo
268 (uint64_t)enc->chroma->u.legacy.level[0].offset_256B * 256); // inputPictureChromaAddressHi/Lo
H A Dradeon_uvd.c1382 return (uint64_t)surface->u.legacy.level[0].offset_256B * 256 +
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_sdma_copy_image.c229 uint64_t dst_address = sdst->buffer.gpu_address + sdst->surface.u.legacy.level[0].offset_256B * 256;
230 uint64_t src_address = ssrc->buffer.gpu_address + ssrc->surface.u.legacy.level[0].offset_256B * 256;
366 linear->surface.u.legacy.level[0].offset_256B * 256;
369 linear->surface.u.legacy.level[0].offset_256B * 256 +
H A Dsi_texture.c151 return (uint64_t)tex->surface.u.legacy.level[level].offset_256B * 256;
155 return (uint64_t)tex->surface.u.legacy.level[level].offset_256B * 256 +
847 i, (uint64_t)tex->surface.u.legacy.level[i].offset_256B * 256,
861 i, (uint64_t)tex->surface.u.legacy.zs.stencil_level[i].offset_256B * 256,
H A Dsi_state.c2605 (tex->buffer.gpu_address >> 8) + tex->surface.u.legacy.level[level].offset_256B;
2607 (tex->buffer.gpu_address >> 8) + tex->surface.u.legacy.zs.stencil_level[level].offset_256B;
3209 cb_color_base += level_info->offset_256B;
H A Dsi_descriptors.c309 va += (uint64_t)base_level_info->offset_256B * 256;
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/
H A Dradeon_video.c183 surfaces[i]->u.legacy.level[j].offset_256B += off / 256;
H A Dr600_state.c763 view->tex_resource_words[2] = tmp->surface.u.legacy.level[offset_level].offset_256B;
765 view->tex_resource_words[3] = tmp->surface.u.legacy.level[offset_level].offset_256B;
767 view->tex_resource_words[3] = tmp->surface.u.legacy.level[offset_level + 1].offset_256B;
832 offset = (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256;
1049 offset = (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256;
2892 base = (uint64_t)rsrc->surface.u.legacy.level[src_level].offset_256B * 256;
2893 addr = (uint64_t)rdst->surface.u.legacy.level[dst_level].offset_256B * 256;
2911 base = (uint64_t)rdst->surface.u.legacy.level[dst_level].offset_256B * 256;
2912 addr = (uint64_t)rsrc->surface.u.legacy.level[src_level].offset_256B * 256;
3015 src_offset= (uint64_t)rsrc->surface.u.legacy.level[src_level].offset_256B * 25
[all...]
H A Dr600_texture.c186 return (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256;
190 return (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256 +
265 surface->u.legacy.level[i].offset_256B += offset / 256;
458 offset = (uint64_t)rtex->surface.u.legacy.level[0].offset_256B * 256;
868 i, (uint64_t)rtex->surface.u.legacy.level[i].offset_256B * 256,
886 i, (uint64_t)rtex->surface.u.legacy.zs.stencil_level[i].offset_256B * 256,
H A Devergreen_state.c855 tex_resource_words[2] = ((uint64_t)surflevel[base_level].offset_256B * 256 + va) >> 8;
869 tex_resource_words[3] = ((uint64_t)surflevel[1].offset_256B * 256 + va) >> 8;
871 tex_resource_words[3] = ((uint64_t)surflevel[base_level].offset_256B * 256 + va) >> 8;
1132 color->offset = (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256;
1369 offset += (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256;
1419 stencil_offset = (uint64_t)rtex->surface.u.legacy.zs.stencil_level[level].offset_256B * 256;
3821 base = (uint64_t)rsrc->surface.u.legacy.level[src_level].offset_256B * 256;
3822 addr = (uint64_t)rdst->surface.u.legacy.level[dst_level].offset_256B * 256;
3846 base = (uint64_t)rdst->surface.u.legacy.level[dst_level].offset_256B * 256;
3847 addr = (uint64_t)rsrc->surface.u.legacy.level[src_level].offset_256B * 25
[all...]
H A Dradeon_uvd.c1173 return (uint64_t)surface->u.legacy.level[0].offset_256B * 256 +
/xsrc/external/mit/MesaLib/dist/src/gallium/winsys/radeon/drm/
H A Dradeon_drm_surface.c70 level_drm->offset = (uint64_t)level_ws->offset_256B * 256;
82 level_ws->offset_256B = level_drm->offset / 256;
/xsrc/external/mit/MesaLib/dist/src/amd/common/
H A Dac_surface.h93 uint32_t offset_256B; /* divided by 256, the hw can only do 40-bit addresses */ member in struct:legacy_surf_level
H A Dac_surface.c635 surf_level->offset_256B = align64(surf->surf_size, AddrSurfInfoOut->baseAlign) / 256;
673 surf->surf_size = (uint64_t)surf_level->offset_256B * 256 + AddrSurfInfoOut->surfSize;
2618 offset = (uint64_t)surf->u.legacy.level[0].offset_256B * 256;
2748 metadata[10 + i] = surf->u.legacy.level[i].offset_256B;
2824 surf->u.legacy.level[i].offset_256B += offset / 256;
2865 return (uint64_t)surf->u.legacy.level[0].offset_256B * 256 +
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_image.c740 va += (uint64_t)base_level_info->offset_256B * 256;
2300 pLayout->offset = (uint64_t)surface->u.legacy.level[level].offset_256B * 256 +
H A Dradv_formats.c1940 .offset_256B * 256;
H A Dradv_device.c4355 offset = (uint64_t)surface->u.legacy.level[level].offset_256B * 256 +
6641 cb->cb_color_base += level_info->offset_256B;
6992 z_offs += (uint64_t)surf->u.legacy.level[level].offset_256B * 256;
6993 s_offs += (uint64_t)surf->u.legacy.zs.stencil_level[level].offset_256B * 256;
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D21.1.0.rst3592 - ac/surface: change legacy_surf_level::offset to 32-bit offset_256B shifted by 8

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