Searched refs:operand1 (Results 1 - 14 of 14) sorted by relevance

/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Di915_3d.h389 #define i915_fs_arith_masked(op, dest_reg, dest_mask, operand0, operand1, operand2) \
390 _i915_fs_arith_masked(A0_##op, dest_reg, dest_mask, operand0, operand1, operand2)
392 #define i915_fs_arith(op, dest_reg, operand0, operand1, operand2) \
393 _i915_fs_arith(A0_##op, dest_reg, operand0, operand1, operand2)
395 #define _i915_fs_arith_masked(cmd, dest_reg, dest_mask, operand0, operand1, operand2) \
419 (REG_TYPE(operand1) << A1_SRC1_TYPE_SHIFT) | \
420 (REG_NR(operand1) << A1_SRC1_NR_SHIFT) | \
421 i915_get_hardware_channel_val(REG_X(operand1), \
424 i915_get_hardware_channel_val(REG_Y(operand1), \
427 OUT_BATCH(i915_get_hardware_channel_val(REG_Z(operand1), \
[all...]
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Di915_3d.h389 #define i915_fs_arith_masked(op, dest_reg, dest_mask, operand0, operand1, operand2) \
390 _i915_fs_arith_masked(A0_##op, dest_reg, dest_mask, operand0, operand1, operand2)
392 #define i915_fs_arith(op, dest_reg, operand0, operand1, operand2) \
393 _i915_fs_arith(A0_##op, dest_reg, operand0, operand1, operand2)
395 #define _i915_fs_arith_masked(cmd, dest_reg, dest_mask, operand0, operand1, operand2) \
419 (REG_TYPE(operand1) << A1_SRC1_TYPE_SHIFT) | \
420 (REG_NR(operand1) << A1_SRC1_NR_SHIFT) | \
421 i915_get_hardware_channel_val(REG_X(operand1), \
424 i915_get_hardware_channel_val(REG_Y(operand1), \
427 OUT_BATCH(i915_get_hardware_channel_val(REG_Z(operand1), \
[all...]
/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di915_3d.h266 #define i915_fs_arith(op, dest_reg, operand0, operand1, operand2) \
267 _i915_fs_arith(A0_##op, dest_reg, operand0, operand1, operand2)
272 struct i915_fs_operand operand1,
312 op.ui[1] |= REG_TYPE(operand1.reg) << A1_SRC1_TYPE_SHIFT;
313 op.ui[1] |= REG_NR(operand1.reg) << A1_SRC1_NR_SHIFT;
315 op.ui[1] |= i915_get_hardware_channel_val(operand1.x) <<
317 if (operand1.x < 0)
320 op.ui[1] |= i915_get_hardware_channel_val(operand1.y) <<
322 if (operand1.y < 0)
325 op.ui[2] |= i915_get_hardware_channel_val(operand1
270 _i915_fs_arith(int cmd,int dest_reg,struct i915_fs_operand operand0,struct i915_fs_operand operand1,struct i915_fs_operand operand2) argument
[all...]
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen3_render.h1236 #define gen3_fs_arith_masked(op, dest_reg, dest_mask, operand0, operand1, operand2) \
1237 _gen3_fs_arith_masked(A0_##op, dest_reg, dest_mask, operand0, operand1, operand2)
1239 #define gen3_fs_arith(op, dest_reg, operand0, operand1, operand2) \
1240 _gen3_fs_arith(A0_##op, dest_reg, operand0, operand1, operand2)
1242 #define _gen3_fs_arith_masked(cmd, dest_reg, dest_mask, operand0, operand1, operand2) \
1266 (REG_TYPE(operand1) << A1_SRC1_TYPE_SHIFT) | \
1267 (REG_NR(operand1) << A1_SRC1_NR_SHIFT) | \
1268 gen3_get_hardware_channel_val(REG_X(operand1), \
1271 gen3_get_hardware_channel_val(REG_Y(operand1), \
1274 OUT_BATCH(gen3_get_hardware_channel_val(REG_Z(operand1), \
[all...]
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dgen3_render.h1236 #define gen3_fs_arith_masked(op, dest_reg, dest_mask, operand0, operand1, operand2) \
1237 _gen3_fs_arith_masked(A0_##op, dest_reg, dest_mask, operand0, operand1, operand2)
1239 #define gen3_fs_arith(op, dest_reg, operand0, operand1, operand2) \
1240 _gen3_fs_arith(A0_##op, dest_reg, operand0, operand1, operand2)
1242 #define _gen3_fs_arith_masked(cmd, dest_reg, dest_mask, operand0, operand1, operand2) \
1266 (REG_TYPE(operand1) << A1_SRC1_TYPE_SHIFT) | \
1267 (REG_NR(operand1) << A1_SRC1_NR_SHIFT) | \
1268 gen3_get_hardware_channel_val(REG_X(operand1), \
1271 gen3_get_hardware_channel_val(REG_Y(operand1), \
1274 OUT_BATCH(gen3_get_hardware_channel_val(REG_Z(operand1), \
[all...]
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/zink/nir_to_spirv/
H A Dspirv_builder.h205 SpvId operand0, SpvId operand1);
209 SpvId operand0, SpvId operand1, SpvId operand2);
213 SpvId operand0, SpvId operand1, SpvId operand2, SpvId operand3);
217 SpvId operand0, SpvId operand1, SpvId operand2, SpvId operand3,
H A Dspirv_builder.c506 SpvId operand0, SpvId operand1)
514 spirv_buffer_emit_word(&b->instructions, operand1);
520 SpvId operand0, SpvId operand1, SpvId operand2)
528 spirv_buffer_emit_word(&b->instructions, operand1);
535 SpvId operand0, SpvId operand1, SpvId operand2, SpvId operand3)
543 spirv_buffer_emit_word(&b->instructions, operand1);
551 SpvId operand0, SpvId operand1, SpvId operand2, SpvId operand3,
560 spirv_buffer_emit_word(&b->instructions, operand1);
505 spirv_builder_emit_binop(struct spirv_builder * b,SpvOp op,SpvId result_type,SpvId operand0,SpvId operand1) argument
519 spirv_builder_emit_triop(struct spirv_builder * b,SpvOp op,SpvId result_type,SpvId operand0,SpvId operand1,SpvId operand2) argument
534 spirv_builder_emit_quadop(struct spirv_builder * b,SpvOp op,SpvId result_type,SpvId operand0,SpvId operand1,SpvId operand2,SpvId operand3) argument
550 spirv_builder_emit_hexop(struct spirv_builder * b,SpvOp op,SpvId result_type,SpvId operand0,SpvId operand1,SpvId operand2,SpvId operand3,SpvId operand4,SpvId operand5) argument
/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/
H A Dbrw_defines.h1459 #define MI_MATH_ALU2(opcode, operand1, operand2) \
1460 ( ((MI_MATH_OPCODE_##opcode) << 20) | ((MI_MATH_OPERAND_##operand1) << 10) | \
1463 #define MI_MATH_ALU1(opcode, operand1) \
1464 ( ((MI_MATH_OPCODE_##opcode) << 20) | ((MI_MATH_OPERAND_##operand1) << 10) )
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/
H A Dbrw_defines.h1463 #define MI_MATH_ALU2(opcode, operand1, operand2) \
1464 ( ((MI_MATH_OPCODE_##opcode) << 20) | ((MI_MATH_OPERAND_##operand1) << 10) | \
1467 #define MI_MATH_ALU1(opcode, operand1) \
1468 ( ((MI_MATH_OPCODE_##opcode) << 20) | ((MI_MATH_OPERAND_##operand1) << 10) )
/xsrc/external/mit/MesaLib.old/dist/src/intel/common/
H A Dgen_mi_builder.h519 _gen_mi_pack_alu(uint32_t opcode, uint32_t operand1, uint32_t operand2) argument
523 .Operand1 = operand1,
/xsrc/external/mit/MesaLib/dist/src/intel/common/
H A Dmi_builder.h701 _mi_pack_alu(uint32_t opcode, uint32_t operand1, uint32_t operand2) argument
705 .Operand1 = operand1,
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/svga/
H A Dsvga_tgsi_vgpu10.c1020 VGPU10OperandToken1 operand1; local in function:emit_src_register
1084 operand0.value = operand1.value = 0;
1120 operand1.extendedOperandType = VGPU10_EXTENDED_OPERAND_MODIFIER;
1122 operand1.operandModifier = VGPU10_OPERAND_MODIFIER_ABS;
1124 operand1.operandModifier = VGPU10_OPERAND_MODIFIER_NEG;
1126 operand1.operandModifier = VGPU10_OPERAND_MODIFIER_ABSNEG;
1133 emit_dword(emit, operand1.value);
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/svga/
H A Dsvga_tgsi_vgpu10.c1491 VGPU10OperandToken1 operand1; local in function:emit_src_register
1493 operand0.value = operand1.value = 0;
1794 operand1.extendedOperandType = VGPU10_EXTENDED_OPERAND_MODIFIER;
1796 operand1.operandModifier = VGPU10_OPERAND_MODIFIER_ABS;
1798 operand1.operandModifier = VGPU10_OPERAND_MODIFIER_NEG;
1800 operand1.operandModifier = VGPU10_OPERAND_MODIFIER_ABSNEG;
1807 emit_dword(emit, operand1.value);
/xsrc/external/mit/MesaLib.old/dist/src/intel/vulkan/
H A DgenX_cmd_buffer.c546 mi_alu(uint32_t opcode, uint32_t operand1, uint32_t operand2) argument
550 .Operand1 = operand1,

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