Searched refs:per_slot_offset (Results 1 - 8 of 8) sorted by relevance
| /xsrc/external/mit/MesaLib.old/dist/src/intel/compiler/ |
| H A D | brw_vec4_gs_visitor.cpp | 253 * per_slot_offset=true, which means that DWORDs 3 and 4 of the message 367 src_reg per_slot_offset(this, glsl_type::uint_type); local in function:brw::vec4_gs_visitor::emit_control_data_bits 368 emit(SHR(dst_reg(per_slot_offset), dword_index, brw_imm_ud(2u))); 369 emit(GS_OPCODE_SET_WRITE_OFFSET, mrf_reg, per_slot_offset,
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| H A D | brw_fs_nir.cpp | 2101 fs_reg channel_mask, per_slot_offset; local in function:fs_visitor::emit_gs_control_data_bits 2110 per_slot_offset = vgrf(glsl_type::uint_type); 2130 if (per_slot_offset.file != BAD_FILE) { 2134 abld.SHR(per_slot_offset, dword_index, brw_imm_ud(2u)); 2151 if (per_slot_offset.file != BAD_FILE) 2158 if (per_slot_offset.file != BAD_FILE) 2159 sources[i++] = per_slot_offset;
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| /xsrc/external/mit/MesaLib/dist/src/intel/compiler/ |
| H A D | brw_vec4_gs_visitor.cpp | 236 * per_slot_offset=true, which means that DWORDs 3 and 4 of the message 344 src_reg per_slot_offset(this, glsl_type::uint_type); local in function:brw::vec4_gs_visitor::emit_control_data_bits 345 emit(SHR(dst_reg(per_slot_offset), dword_index, brw_imm_ud(2u))); 346 emit(GS_OPCODE_SET_WRITE_OFFSET, mrf_reg, per_slot_offset,
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| H A D | brw_fs_nir.cpp | 2282 fs_reg channel_mask, per_slot_offset; local in function:fs_visitor::emit_gs_control_data_bits 2291 per_slot_offset = vgrf(glsl_type::uint_type); 2311 if (per_slot_offset.file != BAD_FILE) { 2315 abld.SHR(per_slot_offset, dword_index, brw_imm_ud(2u)); 2332 if (per_slot_offset.file != BAD_FILE) 2339 if (per_slot_offset.file != BAD_FILE) 2340 sources[i++] = per_slot_offset;
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| /xsrc/external/mit/xf86-video-intel/dist/src/sna/brw/ |
| H A D | brw_eu.h | 960 unsigned per_slot_offset:1; member in struct:brw_instruction::__anon0c137b5d100a::__anon0c137b5d2008
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| H A D | brw_eu_emit.c | 500 /* per_slot_offset = 0 makes it ignore offsets in message header */ 501 insn->bits3.urb_gen7.per_slot_offset = 0;
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| /xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/brw/ |
| H A D | brw_eu.h | 960 unsigned per_slot_offset:1; member in struct:brw_instruction::__anon2bd0c611100a::__anon2bd0c6112008
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| H A D | brw_eu_emit.c | 500 /* per_slot_offset = 0 makes it ignore offsets in message header */ 501 insn->bits3.urb_gen7.per_slot_offset = 0;
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