Searched refs:pipe_config (Results 1 - 25 of 28) sorted by relevance

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/xsrc/external/mit/MesaLib.old/dist/src/amd/addrlib/src/chip/r800/
H A Dsi_gb_reg.h107 unsigned int pipe_config : 5; member in struct:_GB_TILE_MODE_T
137 unsigned int pipe_config : 5; member in struct:_GB_TILE_MODE_T
/xsrc/external/mit/MesaLib/dist/src/amd/addrlib/src/chip/r800/
H A Dsi_gb_reg.h107 unsigned int pipe_config : 5; member in struct:_GB_TILE_MODE_T
140 unsigned int pipe_config : 5; member in struct:_GB_TILE_MODE_T
/xsrc/external/mit/MesaLib/dist/src/freedreno/vulkan/
H A Dtu_util.c184 assert(max_pipe_count <= ARRAY_SIZE(fb->pipe_config));
198 fb->pipe_config[n] = A6XX_VSC_PIPE_CONFIG_REG_X(pipe_x) |
206 memset(fb->pipe_config + used_pipe_count, 0,
H A Dtu_private.h1575 uint32_t pipe_config[MAX_VSC_PIPES]; member in struct:tu_framebuffer
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_dma.c112 unsigned pipe_config; local in function:si_dma_copy_tile
151 pipe_config = G_009910_PIPE_CONFIG(tile_mode);
169 radeon_emit(cs, (slice_tile_max << 0) | (pipe_config << 26));
H A Dsi_texture.c361 surf->u.legacy.pipe_config = metadata->u.legacy.pipe_config;
646 md.u.legacy.pipe_config = surface->u.legacy.pipe_config;
1126 tex->surface.u.legacy.tile_split, tex->surface.u.legacy.pipe_config,
/xsrc/external/mit/MesaLib.old/dist/src/amd/common/
H A Dac_surface.h100 unsigned pipe_config:5; /* max 17 */ member in struct:legacy_surf_layout
H A Dac_surface.c513 surf->u.legacy.pipe_config = csio->pTileInfo->pipeConfig - 1;
787 AddrTileInfoIn.pipeConfig = surf->u.legacy.pipe_config + 1; /* +1 compared to GB_TILE_MODE */
/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
H A Dradv_radeon_winsys.h141 unsigned pipe_config; member in struct:radeon_bo_metadata::__anon996f74f1010a::__anon996f74f10208
H A Dradv_image.c752 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_radeon_winsys.h133 unsigned pipe_config; member in struct:radeon_bo_metadata::__anonc88d74e4010a::__anonc88d74e40208
H A Dradv_image.c433 surface->u.legacy.pipe_config = md->u.legacy.pipe_config;
1286 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeon/
H A Dradeon_winsys.h208 unsigned pipe_config; member in struct:radeon_bo_metadata::__anonaf1fea34010a::__anonaf1fea340208
/xsrc/external/mit/MesaLib/dist/src/amd/common/
H A Dac_surface.h119 unsigned pipe_config : 5; /* max 17 */ member in struct:legacy_surf_layout
H A Dac_surface.c847 surf->u.legacy.pipe_config = csio->pTileInfo->pipeConfig - 1;
1118 AddrTileInfoIn.pipeConfig = surf->u.legacy.pipe_config + 1; /* +1 compared to GB_TILE_MODE */
2530 surf->u.legacy.pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2583 *tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG, surf->u.legacy.pipe_config);
2977 surf->u.legacy.tile_split, surf->u.legacy.pipe_config,
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeon/
H A Dradeon_winsys.h227 unsigned pipe_config; member in struct:radeon_bo_metadata::__anonf1261ac7010a::__anonf1261ac70208
/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/winsys/amdgpu/
H A Dradv_amdgpu_bo.c671 tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG, md->u.legacy.pipe_config);
716 md->u.legacy.pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/
H A Dr600_texture.c284 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
300 surf->u.legacy.pipe_config = metadata->u.legacy.pipe_config;
847 rtex->surface.u.legacy.tile_split, rtex->surface.u.legacy.pipe_config,
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/
H A Dr600_texture.c283 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
299 surf->u.legacy.pipe_config = metadata->u.legacy.pipe_config;
842 rtex->surface.u.legacy.tile_split, rtex->surface.u.legacy.pipe_config,
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/winsys/amdgpu/
H A Dradv_amdgpu_bo.c933 tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG, md->u.legacy.pipe_config);
981 md->u.legacy.pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
/xsrc/external/mit/MesaLib.old/dist/src/freedreno/vulkan/
H A Dtu_cmd_buffer.c224 assert(max_pipe_count <= ARRAY_SIZE(tiling->pipe_config));
238 tiling->pipe_config[n] = A6XX_VSC_PIPE_CONFIG_REG_X(pipe_x) |
246 memset(tiling->pipe_config + used_pipe_count, 0,
H A Dtu_private.h806 uint32_t pipe_config[MAX_VSC_PIPES]; member in struct:tu_tiling_config
/xsrc/external/mit/MesaLib.old/dist/src/gallium/winsys/amdgpu/drm/
H A Damdgpu_bo.c1244 md->u.legacy.pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1280 tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG, md->u.legacy.pipe_config);
/xsrc/external/mit/MesaLib.old/dist/src/amd/addrlib/src/r800/
H A Dciaddrlib.cpp1591 pCfg->info.pipeConfig = static_cast<AddrPipeCfg>(gbTileMode.f.pipe_config + 1);
/xsrc/external/mit/MesaLib/dist/src/amd/addrlib/src/r800/
H A Dciaddrlib.cpp1596 pCfg->info.pipeConfig = static_cast<AddrPipeCfg>(gbTileMode.f.pipe_config + 1);

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