Searched refs:prev_inst (Results 1 - 11 of 11) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/intel/compiler/
H A Dbrw_dead_control_flow.cpp50 backend_instruction *const prev_inst = prev_block->end(); local in function:dead_control_flow_eliminate
56 prev_inst->opcode == BRW_OPCODE_ELSE) {
58 backend_instruction *const else_inst = prev_inst;
63 prev_inst->opcode == BRW_OPCODE_IF) {
67 backend_instruction *const if_inst = prev_inst;
100 prev_inst->opcode == BRW_OPCODE_IF) {
102 backend_instruction *const if_inst = prev_inst;
H A Dbrw_vec4_reg_allocate.cpp316 for (vec4_instruction *prev_inst = (vec4_instruction *) inst->prev; local in function:brw::can_use_scratch_for_source
317 !prev_inst->is_head_sentinel();
318 prev_inst = (vec4_instruction *) prev_inst->prev) {
324 if (prev_inst->dst.file == VGRF && prev_inst->dst.nr == scratch_reg) {
325 return (!prev_inst->predicate || prev_inst->opcode == BRW_OPCODE_SEL) &&
327 ~prev_inst->dst.writemask) == 0;
334 if (prev_inst
[all...]
H A Dbrw_fs.cpp3447 fs_inst *prev_inst = last_mrf_move[inst->dst.nr]; local in function:fs_visitor::remove_duplicate_mrf_writes
3448 if (prev_inst && prev_inst->opcode == BRW_OPCODE_MOV &&
3449 inst->dst.equals(prev_inst->dst) &&
3450 inst->src[0].equals(prev_inst->src[0]) &&
3451 inst->saturate == prev_inst->saturate &&
3452 inst->predicate == prev_inst->predicate &&
3453 inst->conditional_mod == prev_inst->conditional_mod &&
3454 inst->exec_size == prev_inst->exec_size) {
/xsrc/external/mit/MesaLib/dist/src/intel/compiler/
H A Dbrw_dead_control_flow.cpp52 backend_instruction *const prev_inst = prev_block->end(); local in function:dead_control_flow_eliminate
58 prev_inst->opcode == BRW_OPCODE_ELSE) {
60 backend_instruction *const else_inst = prev_inst;
65 prev_inst->opcode == BRW_OPCODE_IF) {
69 backend_instruction *const if_inst = prev_inst;
102 prev_inst->opcode == BRW_OPCODE_IF) {
104 backend_instruction *const if_inst = prev_inst;
H A Dbrw_vec4_reg_allocate.cpp275 for (vec4_instruction *prev_inst = (vec4_instruction *) inst->prev; local in function:brw::can_use_scratch_for_source
276 !prev_inst->is_head_sentinel();
277 prev_inst = (vec4_instruction *) prev_inst->prev) {
283 if (prev_inst->dst.file == VGRF && prev_inst->dst.nr == scratch_reg) {
284 return (!prev_inst->predicate || prev_inst->opcode == BRW_OPCODE_SEL) &&
286 ~prev_inst->dst.writemask) == 0;
293 if (prev_inst
[all...]
H A Dbrw_fs.cpp3571 fs_inst *prev_inst = last_mrf_move[inst->dst.nr]; local in function:fs_visitor::remove_duplicate_mrf_writes
3572 if (prev_inst && prev_inst->opcode == BRW_OPCODE_MOV &&
3573 inst->dst.equals(prev_inst->dst) &&
3574 inst->src[0].equals(prev_inst->src[0]) &&
3575 inst->saturate == prev_inst->saturate &&
3576 inst->predicate == prev_inst->predicate &&
3577 inst->conditional_mod == prev_inst->conditional_mod &&
3578 inst->exec_size == prev_inst->exec_size) {
/xsrc/external/mit/MesaLib/dist/src/broadcom/compiler/
H A Dqpu_schedule.c1021 struct schedule_node *prev_inst)
1029 if (prev_inst) {
1030 if (prev_inst->inst->qpu.sig.thrsw)
1124 if (prev_inst) {
1131 if (prev_inst->inst->uniform != -1 &&
1140 if (vir_has_uniform(prev_inst->inst) &&
1145 if ((prev_inst->inst->qpu.sig.ldunifa ||
1146 prev_inst->inst->qpu.sig.ldunifarf) &&
1172 &prev_inst->inst->qpu, inst)) {
1181 if (prev_inst)
1019 choose_instruction_to_schedule(struct v3d_compile * c,struct choose_scoreboard * scoreboard,struct schedule_node * prev_inst) argument
1853 struct qinst *prev_inst = (struct qinst *) inst->link.prev; local in function:emit_branch
[all...]
H A Dvir.c1872 struct qinst *prev_inst = NULL; local in function:try_opt_ldunif
1895 prev_inst = inst;
1903 if (!prev_inst)
1907 list_for_each_entry_from(struct qinst, inst, prev_inst->link.next,
1909 if (inst->dst.file == prev_inst->dst.file &&
1910 inst->dst.index == prev_inst->dst.index) {
1915 *unif = prev_inst->dst;
/xsrc/external/mit/MesaLib.old/dist/src/broadcom/compiler/
H A Dqpu_schedule.c696 struct schedule_node *prev_inst)
704 if (prev_inst) {
705 if (prev_inst->inst->qpu.sig.thrsw)
759 if (prev_inst) {
766 if (prev_inst->inst->uniform != -1 &&
780 &prev_inst->inst->qpu, inst)) {
1142 vir_for_each_inst_rev(prev_inst, block) {
1143 struct v3d_qpu_sig sig = prev_inst->qpu.sig;
1151 prev_inst, slots_filled + 1,
1156 merge_inst = prev_inst;
694 choose_instruction_to_schedule(const struct v3d_device_info * devinfo,struct choose_scoreboard * scoreboard,struct schedule_node * prev_inst) argument
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/vc4/
H A Dvc4_qpu_schedule.c552 struct schedule_node *prev_inst)
560 if (prev_inst) {
561 uint32_t prev_sig = QPU_GET_FIELD(prev_inst->inst->inst,
602 if (prev_inst) {
611 if (prev_inst->uniform != -1 && n->uniform != -1)
622 inst = qpu_merge_inst(prev_inst->inst->inst, inst);
550 choose_instruction_to_schedule(struct choose_scoreboard * scoreboard,struct list_head * schedule_list,struct schedule_node * prev_inst) argument
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/vc4/
H A Dvc4_qpu_schedule.c552 struct schedule_node *prev_inst)
560 if (prev_inst) {
561 uint32_t prev_sig = QPU_GET_FIELD(prev_inst->inst->inst,
602 if (prev_inst) {
611 if (prev_inst->uniform != -1 && n->uniform != -1)
622 inst = qpu_merge_inst(prev_inst->inst->inst, inst);
550 choose_instruction_to_schedule(struct choose_scoreboard * scoreboard,struct list_head * schedule_list,struct schedule_node * prev_inst) argument

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