Searched refs:radeon_set_uconfig_reg (Results 1 - 24 of 24) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_sqtt.c78 radeon_set_uconfig_reg(
120 radeon_set_uconfig_reg(cs, R_030CDC_SQ_THREAD_TRACE_BASE2,
123 radeon_set_uconfig_reg(cs, R_030CC0_SQ_THREAD_TRACE_BASE, shifted_va);
125 radeon_set_uconfig_reg(cs, R_030CC4_SQ_THREAD_TRACE_SIZE, S_030CC4_SIZE(shifted_size));
127 radeon_set_uconfig_reg(cs, R_030CD4_SQ_THREAD_TRACE_CTRL, S_030CD4_RESET_BUFFER(1));
138 radeon_set_uconfig_reg(cs, R_030CC8_SQ_THREAD_TRACE_MASK, thread_trace_mask);
141 radeon_set_uconfig_reg(
146 radeon_set_uconfig_reg(cs, R_030CD0_SQ_THREAD_TRACE_PERF_MASK,
149 radeon_set_uconfig_reg(cs, R_030CE0_SQ_THREAD_TRACE_TOKEN_MASK2, 0xffffffff);
151 radeon_set_uconfig_reg(c
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H A Dsi_cmd_buffer.c54 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
66 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
107 radeon_set_uconfig_reg(cs, R_0301EC_CP_COHER_START_DELAY,
268 radeon_set_uconfig_reg(cs, R_030964_GE_MAX_VTX_INDX, ~0);
269 radeon_set_uconfig_reg(cs, R_030924_GE_MIN_VTX_INDX, 0);
270 radeon_set_uconfig_reg(cs, R_030928_GE_INDX_OFFSET, 0);
271 radeon_set_uconfig_reg(cs, R_03097C_GE_STEREO_CNTL, 0);
272 radeon_set_uconfig_reg(cs, R_030988_GE_USER_VGPR_EN, 0);
278 radeon_set_uconfig_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0);
279 radeon_set_uconfig_reg(c
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H A Dradv_cs.h152 radeon_set_uconfig_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) function in typeref:typename:void
H A Dradv_device.c3620 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE, S_030938_SIZE(tf_ring_size / 4));
3621 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE, tf_va >> 8);
3624 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3627 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI, S_030944_BASE_HI(tf_va >> 40));
3629 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
H A Dradv_pipeline.c1983 radeon_set_uconfig_reg(
4617 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL, ge_cntl);
5234 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL,
H A Dradv_cmd_buffer.c1656 radeon_set_uconfig_reg(cmd_buffer->cs, R_03098C_GE_VRS_RATE,
1678 radeon_set_uconfig_reg(cmd_buffer->cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
8093 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_sqtt.c98 radeon_set_uconfig_reg(R_030800_GRBM_GFX_INDEX,
145 radeon_set_uconfig_reg(R_030CDC_SQ_THREAD_TRACE_BASE2,
148 radeon_set_uconfig_reg(R_030CC0_SQ_THREAD_TRACE_BASE, shifted_va);
150 radeon_set_uconfig_reg(R_030CC4_SQ_THREAD_TRACE_SIZE,
153 radeon_set_uconfig_reg(R_030CD4_SQ_THREAD_TRACE_CTRL,
164 radeon_set_uconfig_reg(R_030CC8_SQ_THREAD_TRACE_MASK,
168 radeon_set_uconfig_reg(R_030CCC_SQ_THREAD_TRACE_TOKEN_MASK,
174 radeon_set_uconfig_reg(R_030CD0_SQ_THREAD_TRACE_PERF_MASK,
178 radeon_set_uconfig_reg(R_030CE0_SQ_THREAD_TRACE_TOKEN_MASK2, 0xffffffff);
180 radeon_set_uconfig_reg(R_030CEC_SQ_THREAD_TRACE_HIWATE
[all...]
H A Dsi_perfcounter.c84 radeon_set_uconfig_reg(R_030800_GRBM_GFX_INDEX, value);
135 radeon_set_uconfig_reg(R_036020_CP_PERFMON_CNTL,
139 radeon_set_uconfig_reg(R_036020_CP_PERFMON_CNTL,
159 radeon_set_uconfig_reg(
228 radeon_set_uconfig_reg(R_037390_RLC_PERFMON_CLK_CNTL,
231 radeon_set_uconfig_reg(R_0372FC_RLC_PERFMON_CLK_CNTL,
H A Dsi_build_pm4.h132 #define radeon_set_uconfig_reg(reg, value) do { \ macro
254 radeon_set_uconfig_reg(offset, __value); \
H A Dsi_state_streamout.c287 radeon_set_uconfig_reg(reg_strmout_cntl, 0);
H A Dsi_state_shaders.c3661 radeon_set_uconfig_reg(R_030900_VGT_ESGS_RING_SIZE,
3665 radeon_set_uconfig_reg(R_030904_VGT_GSVS_RING_SIZE,
3927 radeon_set_uconfig_reg(R_030938_VGT_TF_RING_SIZE,
3929 radeon_set_uconfig_reg(R_030940_VGT_TF_MEMORY_BASE, factor_va >> 8);
3931 radeon_set_uconfig_reg(R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3934 radeon_set_uconfig_reg(R_030944_VGT_TF_MEMORY_BASE_HI,
3937 radeon_set_uconfig_reg(R_03093C_VGT_HS_OFFCHIP_PARAM,
H A Dsi_state_draw.cpp1240 radeon_set_uconfig_reg(R_03096C_GE_CNTL, ge_cntl);
1272 radeon_set_uconfig_reg(R_030908_VGT_PRIMITIVE_TYPE, vgt_prim);
1284 radeon_set_uconfig_reg(R_03092C_VGT_MULTI_PRIM_IB_RESET_EN, primitive_restart);
H A Dsi_compute.c424 radeon_set_uconfig_reg(R_0301EC_CP_COHER_START_DELAY,
/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
H A Dradv_cs.h108 static inline void radeon_set_uconfig_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) function in typeref:typename:void
H A Dsi_cmd_buffer.c61 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
74 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
245 radeon_set_uconfig_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0);
246 radeon_set_uconfig_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0);
247 radeon_set_uconfig_reg(cs, R_030928_VGT_INDX_OFFSET, 0);
348 radeon_set_uconfig_reg(cs, R_030968_VGT_INSTANCE_BASE_ID, 0);
H A Dradv_device.c2342 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2344 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2347 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2350 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
H A Dradv_cmd_buffer.c2232 radeon_set_uconfig_reg(cs,
5100 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_perfcounter.c561 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX, value);
633 radeon_set_uconfig_reg(cs, *reg++, selectors[idx] | regs->select_or);
635 radeon_set_uconfig_reg(cs, *reg++, 0);
678 radeon_set_uconfig_reg(cs, R_036020_CP_PERFMON_CNTL,
682 radeon_set_uconfig_reg(cs, R_036020_CP_PERFMON_CNTL,
703 radeon_set_uconfig_reg(cs, R_036020_CP_PERFMON_CNTL,
H A Dsi_build_pm4.h96 static inline void radeon_set_uconfig_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) function in typeref:typename:void
H A Dsi_state_streamout.c200 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
H A Dsi_state_draw.c648 radeon_set_uconfig_reg(cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/
H A Dr600_cs.h192 static inline void radeon_set_uconfig_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) function in typeref:typename:void
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/
H A Dr600_cs.h192 static inline void radeon_set_uconfig_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) function in typeref:typename:void
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D21.3.0.rst2707 - radeonsi: remove the unused cs parameter from radeon_set_uconfig_reg

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