Searched refs:rb_aligned (Results 1 - 15 of 15) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/amd/common/
H A Dac_surface_meta_address_test.c60 * bpp, number of fragments, pipe_aligned, rb_aligned */
198 unsigned swizzle_mode, bool pipe_aligned, bool rb_aligned,
215 in.dccKeyFlags.rbAligned = din.dccKeyFlags.rbAligned = rb_aligned;
240 xin.flags.metaRbUnaligned = !rb_aligned;
353 for (int rb_aligned = true; rb_aligned >= (samples > 1 ? true : false); rb_aligned--) { local in function:run_dcc_address_test
360 width, height, depth, bpp, samples, rb_aligned, pipe_aligned);
363 bpp, swizzle_mode, pipe_aligned, rb_aligned, mrt_index,
545 bool pipe_aligned, bool rb_aligned, unsigne
195 one_dcc_address_test(const char * name,const char * test,ADDR_HANDLE addrlib,const struct radeon_info * info,unsigned width,unsigned height,unsigned depth,unsigned samples,unsigned bpp,unsigned swizzle_mode,bool pipe_aligned,bool rb_aligned,unsigned mrt_index,unsigned start_x,unsigned start_y,unsigned start_z,unsigned start_sample) argument
541 one_cmask_address_test(const char * name,const char * test,ADDR_HANDLE addrlib,const struct radeon_info * info,unsigned width,unsigned height,unsigned depth,unsigned bpp,unsigned swizzle_mode,bool pipe_aligned,bool rb_aligned,unsigned mrt_index,unsigned start_x,unsigned start_y,unsigned start_z) argument
660 for (int rb_aligned = true; rb_aligned >= true; rb_aligned--) { local in function:run_cmask_address_test
[all...]
H A Dac_surface_modifier_test.c71 bool rb_aligned, bool pipe_aligned)
87 din.dccKeyFlags.rbAligned = surf->u.gfx9.color.dcc.rb_aligned;
102 dcc_input.dccKeyFlags.rbAligned = rb_aligned;
148 surf->u.gfx9.color.dcc.rb_aligned,
69 get_addr_from_coord_base(ADDR_HANDLE addrlib,const struct radeon_surf * surf,unsigned w,unsigned h,enum pipe_format format,bool rb_aligned,bool pipe_aligned) argument
H A Dac_surface.h159 uint8_t rb_aligned : 1; /* optimal for RBs */ member in struct:gfx9_surf_meta_flags
203 * - rb_aligned
271 /* Displayable DCC. This is always rb_aligned=0 and pipe_aligned=0.
273 * All other chips must set rb_aligned=1.
H A Dac_surface.c1512 const struct radeon_surf *surf, bool rb_aligned,
1523 if (info->use_display_dcc_unaligned && (rb_aligned || pipe_aligned))
1836 surf->u.gfx9.color.dcc.rb_aligned = din.dccKeyFlags.rbAligned;
1911 assert(surf->u.gfx9.color.dcc.pipe_aligned || surf->u.gfx9.color.dcc.rb_aligned);
2278 (!is_dcc_supported_by_DCN(info, config, surf, surf->u.gfx9.color.dcc.rb_aligned,
2295 assert(is_dcc_supported_by_DCN(info, config, surf, surf->u.gfx9.color.dcc.rb_aligned,
2307 is_dcc_supported_by_DCN(info, config, surf, surf->u.gfx9.color.dcc.rb_aligned,
2668 surf->u.gfx9.color.dcc.rb_aligned = G_008F24_META_RB_ALIGNED(desc[5]);
2671 if (!surf->u.gfx9.color.dcc.pipe_aligned && !surf->u.gfx9.color.dcc.rb_aligned)
1510 is_dcc_supported_by_DCN(const struct radeon_info * info,const struct ac_surf_config * config,const struct radeon_surf * surf,bool rb_aligned,bool pipe_aligned) argument
/xsrc/external/mit/MesaLib.old/dist/src/amd/common/
H A Dac_surface.h133 unsigned rb_aligned:1; /* optimal for RBs */ member in struct:gfx9_surf_meta_flags
158 /* Displayable DCC. This is always rb_aligned=0 and pipe_aligned=0.
160 * All other chips must set rb_aligned=1.
H A Dac_surface.c1153 surf->u.gfx9.htile.rb_aligned = hin.hTileFlags.rbAligned;
1220 surf->u.gfx9.dcc.rb_aligned = din.dccKeyFlags.rbAligned;
1275 surf->u.gfx9.dcc.rb_aligned);
1325 addrin.dccKeyFlags.rbAligned = surf->u.gfx9.dcc.rb_aligned;
1447 surf->u.gfx9.cmask.rb_aligned = cin.cMaskFlags.rbAligned;
1650 surf->u.gfx9.dcc.rb_aligned))
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_texture.c739 tex->surface.u.gfx9.dcc.rb_aligned =
744 !tex->surface.u.gfx9.dcc.rb_aligned)
769 !tex->surface.u.gfx9.dcc.rb_aligned)
1086 "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
1090 tex->surface.u.gfx9.cmask.rb_aligned,
1096 "rb_aligned=%u, pipe_aligned=%u\n",
1100 tex->surface.u.gfx9.htile.rb_aligned,
H A Dsi_state.c2592 S_028ABC_RB_ALIGNED(tex->surface.u.gfx9.htile.rb_aligned);
3119 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4019 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
H A Dsi_descriptors.c399 S_008F24_META_RB_ALIGNED(meta.rb_aligned);
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_image.c783 .rb_aligned = 1,
814 .rb_aligned = 1,
823 S_008F24_META_RB_ALIGNED(meta.rb_aligned);
H A Dradv_device.c6621 .rb_aligned = 1,
6630 S_028C74_RB_ALIGNED(meta.rb_aligned) |
/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
H A Dradv_image.c417 S_008F24_META_RB_ALIGNED(meta.rb_aligned);
672 S_008F24_META_RB_ALIGNED(image->planes[0].surface.u.gfx9.cmask.rb_aligned);
H A Dradv_device.c4263 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4545 S_028ABC_RB_ALIGNED(surf->u.gfx9.htile.rb_aligned);
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_descriptors.c354 .rb_aligned = 1,
400 .rb_aligned = 1,
409 S_008F24_META_RB_ALIGNED(meta.rb_aligned);
H A Dsi_state.c3164 .rb_aligned = 1,
3180 S_028C74_RB_ALIGNED(meta.rb_aligned) |

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