Searched refs:readCrtc (Results 1 - 25 of 36) sorted by relevance

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/xsrc/external/mit/xf86-video-openchrome/dist/src/
H A Dvia_id.c42 CARD8 tmp = hwp->readCrtc(hwp, 0x4F);
45 if (hwp->readCrtc(hwp, 0x4F) == 0x55) {
H A Dvia_fp.c562 hwp->writeCrtc(hwp, 0x91, hwp->readCrtc(hwp, 0x91) & 0x7F);
563 hwp->writeCrtc(hwp, 0x91, hwp->readCrtc(hwp, 0x91) | 0x01);
567 hwp->writeCrtc(hwp, 0x91, hwp->readCrtc(hwp, 0x91) | 0x10);
571 hwp->writeCrtc(hwp, 0x91, hwp->readCrtc(hwp, 0x91) | 0x08);
575 hwp->writeCrtc(hwp, 0x91, hwp->readCrtc(hwp, 0x91) | 0x04);
579 hwp->writeCrtc(hwp, 0x91, hwp->readCrtc(hwp, 0x91) | 0x02);
582 hwp->writeCrtc(hwp, 0x91, hwp->readCrtc(hwp, 0x91) & 0xFD);
586 hwp->writeCrtc(hwp, 0x91, hwp->readCrtc(hwp, 0x91) & 0xFB);
590 hwp->writeCrtc(hwp, 0x91, hwp->readCrtc(hwp, 0x91) & 0xF7);
594 hwp->writeCrtc(hwp, 0x91, hwp->readCrtc(hw
[all...]
H A Dvia_vgahw.c101 tmp = hwp->readCrtc(hwp, index);
149 "CR%02X: 0x%02X\n", i, hwp->readCrtc(hwp, i));
152 "CR%02X: 0x%02X\n", i, hwp->readCrtc(hwp, i));
H A Dvia_display.c908 temp = hwp->readCrtc(hwp, 0x36);
911 temp = hwp->readCrtc(hwp, 0x3B);
914 temp = hwp->readCrtc(hwp, 0x3C);
917 temp = hwp->readCrtc(hwp, 0x3D);
920 temp = hwp->readCrtc(hwp, 0x3E);
923 temp = hwp->readCrtc(hwp, 0x3F);
926 temp = hwp->readCrtc(hwp, 0x47);
929 temp = hwp->readCrtc(hwp, 0x6B);
934 temp = hwp->readCrtc(hwp, 0x6C);
1176 temp = hwp->readCrtc(hw
[all...]
H A Dvia_ums.c926 pVia->originalCR3B = hwp->readCrtc(hwp, 0x3B);
927 pVia->originalCR3C = hwp->readCrtc(hwp, 0x3C);
928 pVia->originalCR3D = hwp->readCrtc(hwp, 0x3D);
929 pVia->originalCR3E = hwp->readCrtc(hwp, 0x3E);
930 pVia->originalCR3F = hwp->readCrtc(hwp, 0x3F);
933 pVia->MemClk = hwp->readCrtc(hwp, 0x3D) >> 4;
946 if (hwp->readCrtc(hwp, 0x3B) & 0x02) {
H A Dvia_outputs.c712 tmp = (hwp->readCrtc(hwp, 0x3E) >> 4);
713 tmp |= ((hwp->readCrtc(hwp, 0x3B) & 0x18) << 3);
H A Dvia_analog.c301 CARD8 CR36 = hwp->readCrtc(hwp, 0x36);
/xsrc/external/mit/xf86-video-tseng/dist/src/
H A Dtseng_mode.c1061 tsengReg->CR34 = hwp->readCrtc(hwp, 0x34);
1077 tsengReg->CR33 = hwp->readCrtc(hwp, 0x33);
1078 tsengReg->CR35 = hwp->readCrtc(hwp, 0x35);
1081 tsengReg->CR36 = hwp->readCrtc(hwp, 0x36);
1082 tsengReg->CR37 = hwp->readCrtc(hwp, 0x37);
1083 tsengReg->CR32 = hwp->readCrtc(hwp, 0x32);
1130 tsengReg->CR30 = hwp->readCrtc(hwp, 0x30);
1131 tsengReg->CR31 = hwp->readCrtc(hwp, 0x31);
1132 tsengReg->CR3F = hwp->readCrtc(hwp, 0x3F);
1583 crtc34 |= hwp->readCrtc(hw
[all...]
H A Dtseng_cursor.c188 tmp = hwp->readCrtc(hwp, 0x0E) & 0xF0;
H A Dtseng_driver.c301 tmp = hwp->readCrtc(hwp, 0x11);
314 tmp = hwp->readCrtc(hwp, 0x11);
734 config = hwp->readCrtc(hwp, 0x37);
742 config = hwp->readCrtc(hwp, 0x32);
778 hibit_mode_width = hwp->readCrtc(hwp, 0x01) + 1;
/xsrc/external/mit/xorg-server.old/dist/hw/xfree86/vgahw/
H A DvgaHW.c335 hwp->readCrtc = stdReadCrtc;
542 hwp->readCrtc = mmioReadCrtc;
706 crtc17 |= hwp->readCrtc(hwp, 0x17) & ~0x80;
1027 save->CRTC[i] = hwp->readCrtc(hwp, i);
1805 hwp->writeCrtc(hwp, 0x11, hwp->readCrtc(hwp, 0x11) | 0x80);
1812 hwp->writeCrtc(hwp, 0x11, hwp->readCrtc(hwp, 0x11) & ~0x80);
1939 save->cr03 = hwp->readCrtc(hwp, 0x03);
1941 save->cr12 = hwp->readCrtc(hwp, 0x12);
1943 save->cr15 = hwp->readCrtc(hwp, 0x15);
1945 save->cr10 = hwp->readCrtc(hw
[all...]
H A DvgaHW.h132 vgaHWReadIndexProcPtr readCrtc; member in struct:_vgaHWRec
/xsrc/external/mit/xf86-video-s3virge/dist/src/
H A Ds3v_hwcurs.c57 #define inCRReg(reg) (VGAHWPTR(pScrn))->readCrtc( VGAHWPTR(pScrn), reg )
/xsrc/external/mit/xorg-server/dist/hw/xfree86/vgahw/
H A DvgaHW.c333 hwp->readCrtc = stdReadCrtc;
541 hwp->readCrtc = mmioReadCrtc;
711 crtc17 |= hwp->readCrtc(hwp, 0x17) & ~0x80;
1028 save->CRTC[i] = hwp->readCrtc(hwp, i);
1800 hwp->writeCrtc(hwp, 0x11, hwp->readCrtc(hwp, 0x11) | 0x80);
1807 hwp->writeCrtc(hwp, 0x11, hwp->readCrtc(hwp, 0x11) & ~0x80);
1931 save->cr03 = hwp->readCrtc(hwp, 0x03);
1933 save->cr12 = hwp->readCrtc(hwp, 0x12);
1935 save->cr15 = hwp->readCrtc(hwp, 0x15);
1937 save->cr10 = hwp->readCrtc(hw
[all...]
H A DvgaHW.h130 vgaHWReadIndexProcPtr readCrtc; member in struct:_vgaHWRec
/xsrc/external/mit/xf86-video-i740/dist/src/
H A Di740_driver.c898 i740Reg->ExtVertTotal=hwp->readCrtc(hwp, EXT_VERT_TOTAL);
899 i740Reg->ExtVertDispEnd=hwp->readCrtc(hwp, EXT_VERT_DISPLAY);
900 i740Reg->ExtVertSyncStart=hwp->readCrtc(hwp, EXT_VERT_SYNC_START);
901 i740Reg->ExtVertBlankStart=hwp->readCrtc(hwp, EXT_VERT_BLANK_START);
902 i740Reg->ExtHorizTotal=hwp->readCrtc(hwp, EXT_HORIZ_TOTAL);
903 i740Reg->ExtHorizBlank=hwp->readCrtc(hwp, EXT_HORIZ_BLANK);
904 i740Reg->ExtOffset=hwp->readCrtc(hwp, EXT_OFFSET);
905 i740Reg->InterlaceControl=hwp->readCrtc(hwp, INTERLACE_CNTL);
939 temp=hwp->readCrtc(hwp, VERT_SYNC_END);
1004 temp=hwp->readCrtc(hw
[all...]
/xsrc/external/mit/xf86-video-intel/dist/src/legacy/i810/
H A Di810_driver.c753 i810Reg->IOControl = hwp->readCrtc(hwp, IO_CTNL);
760 i810Reg->ExtVertTotal = hwp->readCrtc(hwp, EXT_VERT_TOTAL);
761 i810Reg->ExtVertDispEnd = hwp->readCrtc(hwp, EXT_VERT_DISPLAY);
762 i810Reg->ExtVertSyncStart = hwp->readCrtc(hwp, EXT_VERT_SYNC_START);
763 i810Reg->ExtVertBlankStart = hwp->readCrtc(hwp, EXT_VERT_BLANK_START);
764 i810Reg->ExtHorizTotal = hwp->readCrtc(hwp, EXT_HORIZ_TOTAL);
765 i810Reg->ExtHorizBlank = hwp->readCrtc(hwp, EXT_HORIZ_BLANK);
766 i810Reg->ExtOffset = hwp->readCrtc(hwp, EXT_OFFSET);
767 i810Reg->InterlaceControl = hwp->readCrtc(hwp, INTERLACE_CNTL);
944 temp = hwp->readCrtc(hw
[all...]
/xsrc/external/mit/xf86-video-intel-2014/dist/src/legacy/i810/
H A Di810_driver.c753 i810Reg->IOControl = hwp->readCrtc(hwp, IO_CTNL);
760 i810Reg->ExtVertTotal = hwp->readCrtc(hwp, EXT_VERT_TOTAL);
761 i810Reg->ExtVertDispEnd = hwp->readCrtc(hwp, EXT_VERT_DISPLAY);
762 i810Reg->ExtVertSyncStart = hwp->readCrtc(hwp, EXT_VERT_SYNC_START);
763 i810Reg->ExtVertBlankStart = hwp->readCrtc(hwp, EXT_VERT_BLANK_START);
764 i810Reg->ExtHorizTotal = hwp->readCrtc(hwp, EXT_HORIZ_TOTAL);
765 i810Reg->ExtHorizBlank = hwp->readCrtc(hwp, EXT_HORIZ_BLANK);
766 i810Reg->ExtOffset = hwp->readCrtc(hwp, EXT_OFFSET);
767 i810Reg->InterlaceControl = hwp->readCrtc(hwp, INTERLACE_CNTL);
944 temp = hwp->readCrtc(hw
[all...]
/xsrc/external/mit/xf86-video-cirrus/dist/src/
H A Dlg_driver.c1044 pCir->chip.lg->SavedReg.ExtVga[CR1A] = hwp->readCrtc(hwp, 0x1A);
1046 pCir->chip.lg->SavedReg.ExtVga[CR1B] = hwp->readCrtc(hwp, 0x1B);
1048 pCir->chip.lg->SavedReg.ExtVga[CR1D] = hwp->readCrtc(hwp, 0x1D);
1050 pCir->chip.lg->SavedReg.ExtVga[CR1E] = hwp->readCrtc(hwp, 0x1E);
1528 cr1D = (hwp->readCrtc(hwp, 0x1D) & ~1) |
1952 tmp = hwp->readCrtc(hwp, 0x1B) & 0xF2;
1956 tmp = hwp->readCrtc(hwp, 0x1D) & 0xE7;
2235 cr1a |= hwp->readCrtc(hwp, 0x1A) & ~0x0C;
2258 hwp->readCrtc = mmioReadCrtc;
H A Dalp_driver.c1135 pCir->chip.alp->ModeReg.ExtVga[CR1A] = pCir->chip.alp->SavedReg.ExtVga[CR1A] = hwp->readCrtc(hwp, 0x1A);
1136 pCir->chip.alp->ModeReg.ExtVga[CR1B] = pCir->chip.alp->SavedReg.ExtVga[CR1B] = hwp->readCrtc(hwp, 0x1B);
1137 pCir->chip.alp->ModeReg.ExtVga[CR1D] = pCir->chip.alp->SavedReg.ExtVga[CR1D] = hwp->readCrtc(hwp, 0x1D);
1778 tmp = hwp->readCrtc(hwp, 0x1B);
1783 tmp = hwp->readCrtc(hwp, 0x1D);
2077 switch (hwp->readCrtc(hwp, 0x2C) >> 6) {
2085 lcdCrtl = hwp->readCrtc(hwp, 0x2D);
2088 switch ((hwp->readCrtc(hwp, 0x9) >> 2) & 3) {
/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di810_driver.c1100 i810Reg->IOControl = hwp->readCrtc(hwp, IO_CTNL);
1107 i810Reg->ExtVertTotal = hwp->readCrtc(hwp, EXT_VERT_TOTAL);
1108 i810Reg->ExtVertDispEnd = hwp->readCrtc(hwp, EXT_VERT_DISPLAY);
1109 i810Reg->ExtVertSyncStart = hwp->readCrtc(hwp, EXT_VERT_SYNC_START);
1110 i810Reg->ExtVertBlankStart = hwp->readCrtc(hwp, EXT_VERT_BLANK_START);
1111 i810Reg->ExtHorizTotal = hwp->readCrtc(hwp, EXT_HORIZ_TOTAL);
1112 i810Reg->ExtHorizBlank = hwp->readCrtc(hwp, EXT_HORIZ_BLANK);
1113 i810Reg->ExtOffset = hwp->readCrtc(hwp, EXT_OFFSET);
1114 i810Reg->InterlaceControl = hwp->readCrtc(hwp, INTERLACE_CNTL);
1291 temp = hwp->readCrtc(hw
[all...]
/xsrc/external/mit/xf86-video-neomagic/dist/src/
H A Dneo.h292 #define VGArCR(index) (*hwp->readCrtc)(hwp, index)
/xsrc/external/mit/xf86-video-savage/dist/src/
H A Dsavage_cursor.c55 #define inCRReg(reg) (VGAHWPTR(pScrn))->readCrtc( VGAHWPTR(pScrn), reg )
/xsrc/external/mit/xf86-video-nv/dist/src/
H A Driva_setup.c206 pVga->readCrtc = RivaReadCrtc;
/xsrc/external/mit/xf86-video-chips/dist/src/
H A Dct_regs.c496 hwp->readCrtc = chipsMmioReadCrtc;

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