Searched refs:set_reg (Results 1 - 6 of 6) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/
H A Dradeon_uvd.c109 static void set_reg(struct ruvd_decoder *dec, unsigned reg, uint32_t val) function in typeref:typename:void
128 set_reg(dec, dec->reg.data0, addr);
129 set_reg(dec, dec->reg.data1, addr >> 32);
132 set_reg(dec, RUVD_GPCOM_VCPU_DATA0, off);
133 set_reg(dec, RUVD_GPCOM_VCPU_DATA1, reloc_idx * 4);
135 set_reg(dec, dec->reg.cmd, cmd << 1);
1018 set_reg(dec, dec->reg.cntl, 1);
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/
H A Dradeon_uvd.c109 static void set_reg(struct ruvd_decoder *dec, unsigned reg, uint32_t val) function in typeref:typename:void
128 set_reg(dec, dec->reg.data0, addr);
129 set_reg(dec, dec->reg.data1, addr >> 32);
132 set_reg(dec, RUVD_GPCOM_VCPU_DATA0, off);
133 set_reg(dec, RUVD_GPCOM_VCPU_DATA1, reloc_idx * 4);
135 set_reg(dec, dec->reg.cmd, cmd << 1);
1261 set_reg(dec, dec->reg.cntl, 1);
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeon/
H A Dradeon_uvd.c105 static void set_reg(struct ruvd_decoder *dec, unsigned reg, uint32_t val) function in typeref:typename:void
124 set_reg(dec, dec->reg.data0, addr);
125 set_reg(dec, dec->reg.data1, addr >> 32);
128 set_reg(dec, RUVD_GPCOM_VCPU_DATA0, off);
129 set_reg(dec, RUVD_GPCOM_VCPU_DATA1, reloc_idx * 4);
131 set_reg(dec, dec->reg.cmd, cmd << 1);
1200 set_reg(dec, dec->reg.cntl, 1);
H A Dradeon_vcn_dec.c994 static void set_reg(struct radeon_decoder *dec, unsigned reg, uint32_t val) function in typeref:typename:void
1012 set_reg(dec, RDECODE_GPCOM_VCPU_DATA0, addr);
1013 set_reg(dec, RDECODE_GPCOM_VCPU_DATA1, addr >> 32);
1014 set_reg(dec, RDECODE_GPCOM_VCPU_CMD, cmd << 1);
1417 set_reg(dec, RDECODE_ENGINE_CNTL, 1);
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeon/
H A Dradeon_uvd.c103 static void set_reg(struct ruvd_decoder *dec, unsigned reg, uint32_t val) function in typeref:typename:void
120 set_reg(dec, dec->reg.data0, addr);
121 set_reg(dec, dec->reg.data1, addr >> 32);
124 set_reg(dec, RUVD_GPCOM_VCPU_DATA0, off);
125 set_reg(dec, RUVD_GPCOM_VCPU_DATA1, reloc_idx * 4);
127 set_reg(dec, dec->reg.cmd, cmd << 1);
1199 set_reg(dec, dec->reg.cntl, 1);
H A Dradeon_vcn_dec.c1858 static void set_reg(struct radeon_decoder *dec, unsigned reg, uint32_t val) function in typeref:typename:void
1874 set_reg(dec, dec->reg.data0, addr);
1875 set_reg(dec, dec->reg.data1, addr >> 32);
1876 set_reg(dec, dec->reg.cmd, cmd << 1);
2294 set_reg(dec, dec->reg.cntl, 1);

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