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  /xsrc/external/mit/MesaLib.old/dist/src/compiler/spirv/
vtn_opencl.c 35 unsigned num_srcs, nir_ssa_def **srcs,
46 nir_ssa_def *srcs[3] = { NULL }; local
47 vtn_assert(num_srcs <= ARRAY_SIZE(srcs));
49 srcs[i] = vtn_ssa_value(b, w[i + 5])->def;
52 nir_ssa_def *result = handler(b, opcode, num_srcs, srcs, dest_type);
109 nir_ssa_def **srcs, const struct glsl_type *dest_type)
112 srcs[0], srcs[1], srcs[2], NULL);
117 nir_ssa_def **srcs, const struct glsl_type *dest_type
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/freedreno/ir3/
ir3_lower_spill.c 44 unsigned orig_components = spill->srcs[2]->uim_val;
50 if (spill->srcs[1]->flags & IR3_REG_ARRAY) {
51 spill->srcs[1]->wrmask = MASK(orig_components);
52 spill->srcs[1]->num = spill->srcs[1]->array.base;
53 spill->srcs[1]->flags &= ~IR3_REG_ARRAY;
63 clone->srcs[1]->wrmask = MASK(components);
64 if (clone->srcs[1]->flags & IR3_REG_ARRAY) {
65 clone->srcs[1]->num = clone->srcs[1]->array.base + comp
    [all...]
ir3_validate.c 117 validate_src(ctx, phi, phi->srcs[pred_idx]);
178 * bindless, irrespective of the precision of other srcs. The
271 if (instr->srcs[0]->flags & IR3_REG_HALF) {
293 validate_reg_size(ctx, instr->srcs[0], instr->cat6.type);
298 validate_assert(ctx, !(instr->srcs[0]->flags & IR3_REG_HALF));
301 validate_assert(ctx, !(instr->srcs[0]->flags & IR3_REG_HALF));
302 validate_assert(ctx, !(instr->srcs[1]->flags & IR3_REG_HALF));
303 validate_reg_size(ctx, instr->srcs[2], instr->cat6.type);
304 validate_assert(ctx, !(instr->srcs[3]->flags & IR3_REG_HALF));
307 validate_assert(ctx, !(instr->srcs[0]->flags & IR3_REG_HALF))
    [all...]
ir3_cp.c 66 struct ir3_register *src = instr->srcs[0];
102 struct ir3_instruction *cond = ssa(cmp->srcs[0]);
104 (cmp->srcs[1]->flags & IR3_REG_IMMED) &&
105 (cmp->srcs[1]->iim_val == 0) &&
116 unsigned srcflags = src->srcs[0]->flags;
150 struct ir3_instruction *srcsrc = ssa(src->srcs[0]);
243 instr->srcs[n] = reg;
282 swap(instr->srcs[0], instr->srcs[1]);
296 ir3_valid_flags(instr, 1, instr->srcs[1]->flags)
    [all...]
ir3_cp_postsched.c 111 struct ir3_register *src = mov->srcs[0];
127 struct ir3_register *src = mov->srcs[0];
169 use->srcs[n] = ir3_reg_clone(mov->block->shader, src);
172 use->srcs[n]->flags |= reg->flags;
177 use->srcs[n]->def = def;
ir3_cf.c 49 struct ir3_register *src = instr->srcs[0];
118 use->srcs[0]->flags |= IR3_REG_HALF;
120 use->srcs[0]->flags &= ~IR3_REG_HALF;
135 /* NOTE: we can have non-ssa srcs after copy propagation: */
136 src = ssa(conv->srcs[0]);
ir3_merge_regs.c 121 value.reg = instr->srcs[0]->def;
128 instr->srcs[value.offset / reg_elem_size(value.reg)];
360 if (phi->srcs[i]->def)
361 try_merge_defs(live, phi->dsts[0], phi->srcs[i]->def, 0);
370 if (!(pcopy->srcs[i]->flags & IR3_REG_SSA))
372 try_merge_defs(live, pcopy->dsts[i], pcopy->srcs[i]->def, 0);
380 try_merge_defs(live, split->srcs[0]->def, split->dsts[0],
389 offset += reg_elem_size(collect->srcs[i]), i++) {
390 if (!(collect->srcs[i]->flags & IR3_REG_SSA))
392 try_merge_defs(live, collect->dsts[0], collect->srcs[i]->def, offset)
    [all...]
ir3_ra_validate.c 237 struct ir3_register *src = split->srcs[0];
256 struct reg_state srcs[size]; local
259 struct ir3_register *src = collect->srcs[i];
263 srcs[dst_offset + j] = (struct reg_state){
269 srcs[dst_offset + j] = file->regs[src_physreg + j];
275 file->regs[dst_physreg + i] = srcs[i];
283 size += reg_size(pcopy->srcs[i]);
286 struct reg_state srcs[size]; local
291 struct ir3_register *src = pcopy->srcs[i];
296 srcs[offset + j] = (struct reg_state)
    [all...]
  /xsrc/external/mit/MesaLib/src/panfrost/bifrost/
bifrost_gen_disasm.c 5 bi_disasm_fma_arshift_i32(FILE *fp, unsigned bits, struct bifrost_regs *srcs, struct bifrost_regs *next_regs, unsigned staging_register, unsigned branch_offset, struct bi_constants *consts, bool last)
17 dump_src(fp, _BITS(bits, 0, 3), *srcs, branch_offset, consts, true);
20 dump_src(fp, _BITS(bits, 3, 3), *srcs, branch_offset, consts, true);
23 dump_src(fp, _BITS(bits, 6, 3), *srcs, branch_offset, consts, true);
28 bi_disasm_fma_arshift_v2i16_0(FILE *fp, unsigned bits, struct bifrost_regs *srcs, struct bifrost_regs *next_regs, unsigned staging_register, unsigned branch_offset, struct bi_constants *consts, bool last)
38 dump_src(fp, _BITS(bits, 0, 3), *srcs, branch_offset, consts, true);
41 dump_src(fp, _BITS(bits, 3, 3), *srcs, branch_offset, consts, true);
44 dump_src(fp, _BITS(bits, 6, 3), *srcs, branch_offset, consts, true);
49 bi_disasm_fma_arshift_v2i16_1(FILE *fp, unsigned bits, struct bifrost_regs *srcs, struct bifrost_regs *next_regs, unsigned staging_register, unsigned branch_offset, struct bi_constants *consts, bool last)
59 dump_src(fp, _BITS(bits, 0, 3), *srcs, branch_offset, consts, true)
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/asahi/compiler/
agx_opcodes.py 29 def __init__(self, name, dests, srcs, imms, is_float, can_eliminate, encoding_16, encoding_32):
32 self.srcs = srcs
60 def op(name, encoding_32, dests = 1, srcs = 0, imms = [], is_float = False, can_eliminate = True, encoding_16 = None):
64 opcodes[name] = Opcode(name, dests, srcs, imms, is_float, can_eliminate, encoding_16, encoding_32)
129 srcs = 1, is_float = True)
149 srcs = 2, is_float = True)
154 srcs = 3, is_float = True)
159 srcs = 2, is_float = True)
168 srcs = 2, imms = [SHIFT]
184 srcs = 2) variable
    [all...]
agx_optimizer.c 94 agx_optimizer_fmov(agx_instr **defs, agx_instr *ins, unsigned srcs)
96 for (unsigned s = 0; s < srcs; ++s) {
110 unsigned srcs, bool is_float)
112 for (unsigned s = 0; s < srcs; ++s) {
  /xsrc/external/mit/MesaLib/dist/src/compiler/glsl/
glsl_to_nir.cpp 89 nir_alu_instr *emit(nir_op op, unsigned dest_size, nir_ssa_def **srcs);
1358 nir_ssa_def *srcs[4]; local
1362 srcs[i] = nir_channel(&b, src_addr, i);
1364 srcs[i] = nir_ssa_undef(&b, 1, 32);
1367 instr->src[1] = nir_src_for_ssa(nir_vec(&b, srcs, 4));
1887 nir_ssa_def *srcs[4]; local
1889 srcs[i] = evaluate_rvalue(ir->operands[i]);
1898 case ir_unop_bit_not: result = nir_inot(&b, srcs[0]); break;
1900 result = nir_inot(&b, srcs[0]);
1903 result = type_is_float(types[0]) ? nir_fneg(&b, srcs[0]
    [all...]
  /xsrc/external/mit/MesaLib.old/dist/src/compiler/glsl/
glsl_to_nir.cpp 86 nir_alu_instr *emit(nir_op op, unsigned dest_size, nir_ssa_def **srcs);
1242 nir_ssa_def *srcs[4]; local
1246 srcs[i] = nir_channel(&b, src_addr, i);
1248 srcs[i] = &instr_undef->def;
1251 instr->src[1] = nir_src_for_ssa(nir_vec(&b, srcs, 4));
1857 nir_ssa_def *srcs[4]; local
1859 srcs[i] = evaluate_rvalue(ir->operands[i]);
1875 case ir_unop_bit_not: result = nir_inot(&b, srcs[0]); break;
1877 result = nir_inot(&b, srcs[0]);
1880 result = type_is_float(types[0]) ? nir_fneg(&b, srcs[0]
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/compiler/spirv/
vtn_opencl.c 36 unsigned num_srcs, nir_ssa_def **srcs,
181 nir_ssa_def **srcs,
201 call->params[param_idx++] = nir_src_for_ssa(srcs[i]);
214 nir_ssa_def *srcs[5] = { NULL }; local
216 vtn_assert(num_srcs <= ARRAY_SIZE(srcs));
220 srcs[i] = ssa->def;
224 nir_ssa_def *result = handler(b, opcode, num_srcs, srcs, src_types, dest_type);
284 unsigned num_srcs, nir_ssa_def **srcs, struct vtn_type **src_types,
288 srcs[0], srcs[1], srcs[2], NULL)
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/panfrost/bifrost/
disassemble.h 38 bi_disasm_fma(FILE *fp, unsigned bits, struct bifrost_regs *srcs, struct bifrost_regs *next_regs, unsigned staging_register, unsigned branch_offset, struct bi_constants *consts, bool first);
40 void bi_disasm_add(FILE *fp, unsigned bits, struct bifrost_regs *srcs, struct bifrost_regs *next_regs, unsigned staging_register, unsigned branch_offset, struct bi_constants *consts, bool first);
45 void dump_src(FILE *fp, unsigned src, struct bifrost_regs srcs, unsigned branch_offset, struct bi_constants *consts, bool isFMA);
disassemble.c 162 static void dump_regs(FILE *fp, struct bifrost_regs srcs, bool first)
164 struct bifrost_reg_ctrl ctrl = DecodeRegCtrl(fp, srcs, first);
167 fprintf(fp, "slot 0: r%u ", get_reg0(srcs));
169 fprintf(fp, "slot 1: r%u ", get_reg1(srcs));
174 fprintf(fp, "slot 2: r%u (write FMA) ", srcs.reg2);
176 fprintf(fp, "slot 2: r%u (write lo FMA) ", srcs.reg2);
178 fprintf(fp, "slot 2: r%u (write hi FMA) ", srcs.reg2);
180 fprintf(fp, "slot 2: r%u (read) ", srcs.reg2);
183 fprintf(fp, "slot 3: r%u (write %s) ", srcs.reg3, slot3_fma);
185 fprintf(fp, "slot 3: r%u (write lo %s) ", srcs.reg3, slot3_fma)
    [all...]
  /xsrc/external/mit/MesaLib.old/dist/src/compiler/nir/
nir_lower_bit_size.c 55 nir_ssa_def *srcs[4] = { NULL, NULL, NULL, NULL }; local
61 srcs[i] = convert_to_bit_size(bld, src, type, bit_size);
63 srcs[i] = src;
68 nir_build_alu(bld, op, srcs[0], srcs[1], srcs[2], srcs[3]);
  /xsrc/external/mit/MesaLib/dist/src/compiler/nir/tests/
builder_tests.cpp 102 nir_ssa_def *srcs[] = { local
107 store_test_val(nir_extract_bits(b, srcs, 2, 24, 1, 64));
118 nir_ssa_def *srcs[] = { local
123 store_test_val(nir_extract_bits(b, srcs, 2, 16, 1, 64));
134 nir_ssa_def *srcs[] = { local
142 store_test_val(nir_extract_bits(b, srcs, 4, 24, 2, 32));
lower_returns_tests.cpp 125 EXPECT_EQ(phi_1->srcs.length(), 2);
126 EXPECT_EQ(phi_2->srcs.length(), 2);
205 EXPECT_EQ(phi_1->srcs.length(), 2);
206 EXPECT_EQ(phi_2->srcs.length(), 2);
  /xsrc/external/mit/MesaLib/dist/src/broadcom/compiler/
vir_opt_redundant_flags.c 52 vir_sources_modified(struct qinst *srcs, struct qinst *write)
54 for (int i = 0; i < vir_get_nsrc(srcs); i++) {
56 srcs->src[i].file == QFILE_TEMP &&
57 srcs->src[i].index == write->dst.index) {
62 if (srcs->src[i].file != QFILE_TEMP &&
63 srcs->src[i].file != QFILE_SMALL_IMM)
  /xsrc/external/mit/MesaLib.old/dist/src/broadcom/compiler/
vir_opt_redundant_flags.c 52 vir_sources_modified(struct qinst *srcs, struct qinst *write)
54 for (int i = 0; i < vir_get_nsrc(srcs); i++) {
56 srcs->src[i].file == QFILE_TEMP &&
57 srcs->src[i].index == write->dst.index) {
62 if (srcs->src[i].file != QFILE_TEMP &&
63 srcs->src[i].file != QFILE_SMALL_IMM)
  /xsrc/external/mit/MesaLib.old/dist/src/intel/compiler/
brw_fs_nir.cpp 2463 const fs_reg srcs[] = { icp_handle, indirect_offset };
2467 bld.LOAD_PAYLOAD(payload, srcs, ARRAY_SIZE(srcs), 0);
2716 const fs_reg srcs[] = { icp_handle, indirect_offset };
2718 bld.LOAD_PAYLOAD(payload, srcs, ARRAY_SIZE(srcs), 0);
2807 const fs_reg srcs[] = {
2812 bld.LOAD_PAYLOAD(payload, srcs, ARRAY_SIZE(srcs), 0);
2844 fs_reg srcs[7]
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/intel/compiler/
brw_fs_nir.cpp 2627 const fs_reg srcs[] = { icp_handle, indirect_offset };
2631 bld.LOAD_PAYLOAD(payload, srcs, ARRAY_SIZE(srcs), 0);
2928 const fs_reg srcs[] = { icp_handle, indirect_offset };
2930 bld.LOAD_PAYLOAD(payload, srcs, ARRAY_SIZE(srcs), 0);
3002 const fs_reg srcs[] = { output_handles, indirect_offset };
3004 bld.LOAD_PAYLOAD(payload, srcs, ARRAY_SIZE(srcs), 0);
3037 fs_reg srcs[7]
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/sfn/
sfn_nir_lower_fs_out_to_vector.cpp 91 nir_ssa_def **srcs, unsigned first_comp, unsigned num_comps) = 0;
104 nir_ssa_def **srcs, unsigned first_comp, unsigned num_comps) override;
107 nir_ssa_def *create_combined_vector(nir_builder *b, nir_ssa_def **srcs,
359 nir_ssa_def *srcs[4]; local
361 srcs[i] = &instr_undef->def;
363 srcs[var->data.location_frac] = intr->src[1].ssa;
378 if (srcs[var2->data.location_frac] == &instr_undef->def) {
381 srcs[var2->data.location_frac] = intr2->src[1].ssa;
386 create_new_io(b, intr, new_var, srcs, new_var->data.location_frac,
398 nir_ssa_def **srcs, unsigned first_comp, unsigned num_comps
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/gallium/auxiliary/gallivm/
lp_bld_conv.h 70 const LLVMValueRef *srcs, unsigned num_srcs,

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