Searched refs:surface_state_pool (Results 1 - 17 of 17) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/intel/vulkan/
H A DgenX_blorp_exec.c67 &cmd_buffer->device->surface_state_pool.block_pool, ss_offset);
87 .buffer = cmd_buffer->device->surface_state_pool.block_pool.bo,
H A Danv_image.c1222 return anv_state_pool_alloc(&device->surface_state_pool, 64, 64);
1689 anv_state_pool_free(&device->surface_state_pool,
1694 anv_state_pool_free(&device->surface_state_pool,
1699 anv_state_pool_free(&device->surface_state_pool,
1704 anv_state_pool_free(&device->surface_state_pool,
1796 anv_state_pool_free(&device->surface_state_pool,
1800 anv_state_pool_free(&device->surface_state_pool,
1804 anv_state_pool_free(&device->surface_state_pool,
H A Danv_batch_chain.c671 struct anv_state_pool *state_pool = &device->surface_state_pool;
688 *state_offset = device->surface_state_pool.block_pool.start_address -
1354 cmd_buffer->device->surface_state_pool.block_pool.bo,
1379 &cmd_buffer->device->surface_state_pool;
H A Danv_cmd_buffer.c185 &device->surface_state_pool, 4096);
278 &cmd_buffer->device->surface_state_pool, 4096);
H A Danv_private.h1131 struct anv_state_pool surface_state_pool; member in struct:anv_device
1167 return &device->surface_state_pool;
1176 return anv_state_pool_alloc_back(&device->surface_state_pool);
H A Danv_descriptor_set.c740 &device->surface_state_pool, 4096);
801 &device->surface_state_pool, 4096);
H A Danv_device.c2080 if (get_bo_from_pool(&ret_bo, &device->surface_state_pool.block_pool, address))
2311 result = anv_state_pool_init(&device->surface_state_pool, device,
2392 anv_state_pool_finish(&device->surface_state_pool);
2452 anv_state_pool_finish(&device->surface_state_pool);
H A DgenX_cmd_buffer.c134 .bo = device->surface_state_pool.block_pool.bo,
838 .bo = cmd_buffer->device->surface_state_pool.block_pool.bo,
1525 primary->device->surface_state_pool.block_pool.bo;
/xsrc/external/mit/MesaLib/dist/src/intel/vulkan/
H A DgenX_blorp_exec.c90 &cmd_buffer->device->surface_state_pool.block_pool, ss_offset, 8);
116 .buffer = cmd_buffer->device->surface_state_pool.block_pool.bo,
H A Danv_image.c2319 return anv_state_pool_alloc(&device->surface_state_pool, 64, 64);
2699 anv_state_pool_free(&device->surface_state_pool,
2704 anv_state_pool_free(&device->surface_state_pool,
2709 anv_state_pool_free(&device->surface_state_pool,
2714 anv_state_pool_free(&device->surface_state_pool,
2805 anv_state_pool_free(&device->surface_state_pool,
2809 anv_state_pool_free(&device->surface_state_pool,
2813 anv_state_pool_free(&device->surface_state_pool,
H A Danv_batch_chain.c1525 anv_bo_unwrap(cmd_buffer->device->surface_state_pool.block_pool.bo);
1564 &cmd_buffer->device->surface_state_pool;
1634 struct anv_state_pool *ss_pool = &device->surface_state_pool;
1734 device->surface_state_pool.block_pool.bo,
H A Danv_allocator.c1430 anv_state_pool_free(&device->surface_state_pool,
1522 anv_state_pool_alloc(&device->surface_state_pool,
1537 anv_state_pool_free(&device->surface_state_pool, state);
H A Danv_device.c2827 if (get_bo_from_pool(&ret_bo, &device->surface_state_pool.block_pool, address))
3175 result = anv_state_pool_init(&device->surface_state_pool, device,
3231 anv_state_pool_alloc(&device->surface_state_pool,
3280 anv_state_pool_finish(&device->surface_state_pool);
3360 anv_state_pool_finish(&device->surface_state_pool);
H A Danv_cmd_buffer.c291 &device->surface_state_pool, 4096);
395 &cmd_buffer->device->surface_state_pool, 4096);
H A Danv_descriptor_set.c888 &device->surface_state_pool, 4096);
947 &device->surface_state_pool, 4096);
H A Danv_private.h1182 struct anv_state_pool surface_state_pool; member in struct:anv_device
1271 return &device->surface_state_pool;
1281 return anv_state_pool_alloc_back(&device->surface_state_pool);
H A DgenX_cmd_buffer.c207 .bo = device->surface_state_pool.block_pool.bo,
1088 .bo = cmd_buffer->device->surface_state_pool.block_pool.bo,
1985 primary->device->surface_state_pool.block_pool.bo;

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