Searched refs:swizzling (Results 1 - 25 of 46) sorted by relevance

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/xsrc/external/mit/MesaLib.old/dist/src/intel/isl/
H A Disl_storage_image.c215 /* Set the swizzling shifts to all-ones to effectively disable
216 * swizzling -- See emit_address_calculation() in
220 .swizzling = { 0xff, 0xff },
278 param->swizzling[0] = 3;
279 param->swizzling[1] = 4;
296 param->swizzling[0] = 3;
297 param->swizzling[1] = 0xff;
/xsrc/external/mit/MesaLib/dist/src/intel/isl/
H A Disl_storage_image.c215 /* Set the swizzling shifts to all-ones to effectively disable
216 * swizzling -- See emit_address_calculation() in
220 .swizzling = { 0xff, 0xff },
282 param->swizzling[0] = 3;
283 param->swizzling[1] = 4;
300 param->swizzling[0] = 3;
301 param->swizzling[1] = 0xff;
/xsrc/external/mit/MesaLib/dist/docs/isl/
H A Dtiling.rst13 Tiling (sometimes referred to as swizzling) is a method of re-arranging the
58 memory controller has a more effective address swizzling algorithm.
60 Whether or not swizzling is enabled depends on the memory configuration of the
61 system. Generally, systems with dual-channel RAM have swizzling enabled and
62 single-channel do not. Supposedly, this swizzling allows for better balancing
67 The best documentation for bit-6 swizzling can be found in the Haswell PRM Vol.
161 When bit-6 swizzling is enabled, bits 9 and 10 are XOR'd in with bit 6 of the
204 When bit-6 swizzling is enabled, bit 9 is XOR'd in with bit 6 of the tiled
H A Dccs.rst75 gathered on a dual-channel system so bit-6 swizzling was enabled. It's unclear
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D8.0.2.rst76 - i965: fixup W-tile offset computation to take swizzling into account
H A D9.1.6.rst97 - i965/vs: Fix flaky texture swizzling
H A D20.0.3.rst93 - intel/blorp: Add support for swizzling fast-clear colors
H A D9.1.2.rst164 - i965: Don't use texture swizzling to force alpha to 1.0 if
H A D9.0.3.rst173 - i965: Do texture swizzling in hardware on Haswell.
H A D9.1.4.rst280 - r300g/compiler: Prevent regalloc from swizzling texture operands v2
H A D7.10.rst274 - llvmpipe: fix swizzling of texture border color
275 - softpipe: fix swizzling of texture border color
1074 - i965: Remove swizzling of assignment to vector-splitting
1149 - i965: Set up swizzling of shadow compare results for
1181 - i965: Enable attribute swizzling (repositioning) in the gen6 SF.
1279 - i965: Work around strangeness in swizzling/masking of gen6 math.
1373 - intel: Set the swizzling for depth textures using the GL_RED depth
2267 - r300g: fix swizzling of texture border color
2316 - r300/compiler: add a function for swizzling a mask
2325 - r300g: fix texture swizzling wit
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H A D7.9.1.rst337 - r300g: fix texture swizzling with compressed textures on r400-r500
/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/
H A Dbrw_nir_uniforms.cpp110 offsetof(brw_image_param, swizzling), 2);
H A Dbrw_wm_surface_state.c324 * swizzling.
1494 /* Set the swizzling shifts to all-ones to effectively disable swizzling --
1498 param->swizzling[0] = 0xff;
1499 param->swizzling[1] = 0xff;
H A DgenX_state_upload.c1043 * do back-facing swizzling.
1045 bool swizzling = two_side_color && local in function:genX
1051 /* Update max_source_attr. If swizzling, the SF will read this slot + 1. */
1052 if (*max_source_attr < source_attr + swizzling)
1053 *max_source_attr = source_attr + swizzling;
1056 if (swizzling)
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dblt.c748 void choose_memcpy_tiled_x(struct kgem *kgem, int swizzling) argument
750 switch (swizzling) {
752 DBG(("%s: unknown swizzling, %d\n", __FUNCTION__, swizzling));
755 DBG(("%s: no swizzling\n", __FUNCTION__));
760 DBG(("%s: 6^9 swizzling\n", __FUNCTION__));
765 DBG(("%s: 6^9^10 swizzling\n", __FUNCTION__));
770 DBG(("%s: 6^9^11 swizzling\n", __FUNCTION__));
H A Dkgem.h855 void choose_memcpy_tiled_x(struct kgem *kgem, int swizzling);
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dblt.c1156 void choose_memcpy_tiled_x(struct kgem *kgem, int swizzling, unsigned cpu) argument
1159 if (swizzling == I915_BIT_6_SWIZZLE_NONE) {
1160 DBG(("%s: gen2, no swizzling\n", __FUNCTION__));
1168 switch (swizzling) {
1170 DBG(("%s: unknown swizzling, %d\n", __FUNCTION__, swizzling));
1173 DBG(("%s: no swizzling\n", __FUNCTION__));
1188 DBG(("%s: 6^9 swizzling\n", __FUNCTION__));
1193 DBG(("%s: 6^9^10 swizzling\n", __FUNCTION__));
1198 DBG(("%s: 6^9^11 swizzling\
[all...]
H A Dkgem.h901 void choose_memcpy_tiled_x(struct kgem *kgem, int swizzling, unsigned cpu);
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/
H A Dbrw_nir_uniforms.cpp110 offsetof(brw_image_param, swizzling), 2);
H A Dbrw_wm_surface_state.c321 * swizzling.
1506 /* Set the swizzling shifts to all-ones to effectively disable swizzling --
1510 param->swizzling[0] = 0xff;
1511 param->swizzling[1] = 0xff;
/xsrc/external/mit/MesaLib.old/dist/src/intel/compiler/
H A Dbrw_compiler.h466 * Right shift to apply for bit 6 address swizzling. Two different
470 * addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
471 * (addr >> swizzling[1])))
475 uint32_t swizzling[2]; member in struct:brw_image_param
/xsrc/external/mit/MesaLib/dist/docs/drivers/
H A Dllvmpipe.rst228 Swizzling <http://devmaster.net/posts/12785/texture-swizzling>`__
/xsrc/external/mit/MesaLib/dist/src/intel/compiler/
H A Dbrw_compiler.h582 * Right shift to apply for bit 6 address swizzling. Two different
586 * addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
587 * (addr >> swizzling[1])))
591 uint32_t swizzling[2]; member in struct:brw_image_param
/xsrc/external/mit/MesaLib/dist/docs/gallium/
H A Dscreen.rst40 * ``PIPE_CAP_TEXTURE_SWIZZLE``: Whether swizzling through sampler views is
176 and swizzling in gallium frontends. Generally, all hardware drivers with
606 * ``PIPE_CAP_VIEWPORT_SWIZZLE``: Whether pipe_viewport_state::swizzle can be used to specify pre-clipping swizzling of coordinates (see GL_NV_viewport_swizzle).

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