Searched refs:tc_compatible_htile (Results 1 - 12 of 12) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_texture.c47 bool tc_compatible_htile);
166 bool is_flushed_depth, bool tc_compatible_htile)
190 } else if (tc_compatible_htile &&
496 tex->tc_compatible_htile = new_tex->tc_compatible_htile;
816 u_log_printf(log, ", tc_compatible_htile=%u", tex->tc_compatible_htile);
930 tex->tc_compatible_htile = (sscreen->info.chip_class == GFX8 &&
1034 if (sscreen->info.chip_class >= GFX9 || tex->tc_compatible_htile)
1144 bool tc_compatible_htile)
163 si_init_surface(struct si_screen * sscreen,struct radeon_surf * surface,const struct pipe_resource * ptex,enum radeon_surf_mode array_mode,uint64_t modifier,bool is_imported,bool is_scanout,bool is_flushed_depth,bool tc_compatible_htile) argument
1142 si_choose_tiling(struct si_screen * sscreen,const struct pipe_resource * templ,bool tc_compatible_htile) argument
1229 bool tc_compatible_htile = local in function:si_texture_create_with_modifier
[all...]
H A Dsi_clear.c525 (!zstex->tc_compatible_htile || depth == 0 || depth == 1);
534 (!zstex->tc_compatible_htile || stencil == 0);
782 assert(!zstex->tc_compatible_htile);
786 zstex->tc_compatible_htile = true;
H A Dsi_pipe.h369 bool tc_compatible_htile : 1; member in struct:si_texture
1815 assert(!tex->tc_compatible_htile || tex->surface.meta_offset);
1816 return tex->tc_compatible_htile && si_htile_enabled(tex, level, zs_mask);
H A Dsi_state.c3347 if (tex->tc_compatible_htile) {
3364 S_02803C_ADDR5_SWIZZLE_MASK(!tex->tc_compatible_htile));
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_texture.c44 const struct pipe_resource *templ, bool tc_compatible_htile);
230 bool tc_compatible_htile)
252 if (tc_compatible_htile &&
586 tex->tc_compatible_htile = new_tex->tc_compatible_htile;
1038 if (sscreen->info.chip_class <= VI && !tex->tc_compatible_htile)
1149 tex->tc_compatible_htile);
1226 tex->tc_compatible_htile = tex->surface.htile_size != 0 &&
1233 if (tex->tc_compatible_htile) {
1354 if (sscreen->info.chip_class >= GFX9 || tex->tc_compatible_htile)
221 si_init_surface(struct si_screen * sscreen,struct radeon_surf * surface,const struct pipe_resource * ptex,enum radeon_surf_mode array_mode,unsigned pitch_in_bytes_override,unsigned offset,bool is_imported,bool is_scanout,bool is_flushed_depth,bool tc_compatible_htile) argument
1492 si_choose_tiling(struct si_screen * sscreen,const struct pipe_resource * templ,bool tc_compatible_htile) argument
1583 bool tc_compatible_htile = local in function:si_texture_create
[all...]
H A Dsi_pipe.h307 bool tc_compatible_htile:1; member in struct:si_texture
1621 assert(!tex->tc_compatible_htile || tex->htile_offset);
1622 return tex->tc_compatible_htile && level == 0;
H A Dsi_clear.c590 (!zstex->tc_compatible_htile ||
610 (!zstex->tc_compatible_htile || stencil == 0)) {
H A Dsi_state.c2566 if (tex->tc_compatible_htile) {
2608 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!tex->tc_compatible_htile);
2658 } else if (!tex->tc_compatible_htile) {
2670 if (tex->tc_compatible_htile) {
3813 tex->tc_compatible_htile)
/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
H A Dradv_private.h1530 bool tc_compatible_htile; member in struct:radv_image
1649 return radv_image_has_htile(image) && image->tc_compatible_htile;
H A Dradv_image.c1086 image->tc_compatible_htile = image->planes[0].surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D20.2.0.rst3209 - radeonsi: allow tc_compatible_htile to be mutable
H A D21.1.0.rst5045 - radv: remove unnecessary radv_image::tc_compatible_htile

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