Searched refs:tcl (Results 1 - 25 of 38) sorted by relevance

12

/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/r200/
H A Dr200_cmdbuf.c75 insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.tcl );
151 OUT_BATCH(rmesa->radeon.tcl.elt_dma_offset);
154 rmesa->radeon.tcl.elt_dma_bo,
163 int nr, elt_used = rmesa->tcl.elt_used;
165 radeon_print(RADEON_RENDER, RADEON_VERBOSE, "%s %x %d\n", __func__, rmesa->tcl.hw_primitive, elt_used);
172 radeon_bo_unmap(rmesa->radeon.tcl.elt_dma_bo);
174 r200FireEB(rmesa, nr, rmesa->tcl.hw_primitive);
176 radeon_bo_unref(rmesa->radeon.tcl.elt_dma_bo);
177 rmesa->radeon.tcl.elt_dma_bo = NULL;
196 radeonAllocDmaRegion(&rmesa->radeon, &rmesa->radeon.tcl
[all...]
H A Dr200_maos_arrays.c115 if (!rmesa->radeon.tcl.aos[i].bo) {
118 &(rmesa->radeon.tcl.aos[nr]),
125 &(rmesa->radeon.tcl.aos[nr]),
174 if (!rmesa->radeon.tcl.aos[nr].bo) {
176 &(rmesa->radeon.tcl.aos[nr]),
195 rmesa->radeon.tcl.aos_count = nr;
H A Dr200_state.c393 R200_STATECHANGE(rmesa, tcl);
394 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~R200_TCL_FOG_MASK;
397 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= R200_TCL_FOG_LINEAR;
408 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= R200_TCL_FOG_EXP;
413 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= R200_TCL_FOG_EXP2;
499 GLuint t = rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL];
526 if ( rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] != t ) {
527 R200_STATECHANGE(rmesa, tcl );
528 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] = t;
540 R200_STATECHANGE( rmesa, tcl );
[all...]
H A Dr200_tcl.c144 rmesa->tcl.elt_used + nr*2 < R200_ELT_BUF_SZ) {
146 GLushort *dest = (GLushort *)(rmesa->radeon.tcl.elt_dma_bo->ptr +
147 rmesa->radeon.tcl.elt_dma_offset + rmesa->tcl.elt_used);
149 rmesa->tcl.elt_used += nr*2;
158 rmesa->radeon.tcl.aos_count, 0 );
160 r200EmitMaxVtxIndex(rmesa, rmesa->radeon.tcl.aos[0].count);
161 return r200AllocEltsOpenEnded( rmesa, rmesa->tcl.hw_primitive, nr );
186 // fprintf(stderr,"Emit prim %d\n", rmesa->radeon.tcl.aos_count);
189 rmesa->radeon.tcl
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H A Dr200_state_init.c57 * the tcl scalar and vector areas.
264 TCL_CHECK( tcl, GL_TRUE, 0 )
709 ALLOC_STATE( tcl, tcl_or_vp, TCL_STATE_SIZE, "TCL/tcl", 0 );
710 ALLOC_STATE( msl, tcl, MSL_STATE_SIZE, "MSL/matrix-select", 0 );
711 ALLOC_STATE( tcg, tcl, TCG_STATE_SIZE, "TCG/texcoordgen", 0 );
809 rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(rmesa, R200_EMIT_TCL_LIGHT_MODEL_CTL_0);
810 rmesa->hw.tcl.cmd[TCL_CMD_1] = cmdpkt(rmesa, R200_EMIT_TCL_UCP_VERT_BLEND_CTL);
1174 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] =
1181 rmesa->hw.tcl
[all...]
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/r200/
H A Dr200_cmdbuf.c75 insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.tcl );
151 OUT_BATCH(rmesa->radeon.tcl.elt_dma_offset);
154 rmesa->radeon.tcl.elt_dma_bo,
163 int nr, elt_used = rmesa->tcl.elt_used;
165 radeon_print(RADEON_RENDER, RADEON_VERBOSE, "%s %x %d\n", __func__, rmesa->tcl.hw_primitive, elt_used);
172 radeon_bo_unmap(rmesa->radeon.tcl.elt_dma_bo);
174 r200FireEB(rmesa, nr, rmesa->tcl.hw_primitive);
176 radeon_bo_unref(rmesa->radeon.tcl.elt_dma_bo);
177 rmesa->radeon.tcl.elt_dma_bo = NULL;
196 radeonAllocDmaRegion(&rmesa->radeon, &rmesa->radeon.tcl
[all...]
H A Dr200_maos_arrays.c115 if (!rmesa->radeon.tcl.aos[i].bo) {
118 &(rmesa->radeon.tcl.aos[nr]),
125 &(rmesa->radeon.tcl.aos[nr]),
173 if (!rmesa->radeon.tcl.aos[nr].bo) {
175 &(rmesa->radeon.tcl.aos[nr]),
194 rmesa->radeon.tcl.aos_count = nr;
H A Dr200_state.c393 R200_STATECHANGE(rmesa, tcl);
394 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~R200_TCL_FOG_MASK;
397 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= R200_TCL_FOG_LINEAR;
408 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= R200_TCL_FOG_EXP;
413 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= R200_TCL_FOG_EXP2;
499 GLuint t = rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL];
526 if ( rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] != t ) {
527 R200_STATECHANGE(rmesa, tcl );
528 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] = t;
540 R200_STATECHANGE( rmesa, tcl );
[all...]
H A Dr200_tcl.c144 rmesa->tcl.elt_used + nr*2 < R200_ELT_BUF_SZ) {
146 GLushort *dest = (GLushort *)(rmesa->radeon.tcl.elt_dma_bo->ptr +
147 rmesa->radeon.tcl.elt_dma_offset + rmesa->tcl.elt_used);
149 rmesa->tcl.elt_used += nr*2;
158 rmesa->radeon.tcl.aos_count, 0 );
160 r200EmitMaxVtxIndex(rmesa, rmesa->radeon.tcl.aos[0].count);
161 return r200AllocEltsOpenEnded( rmesa, rmesa->tcl.hw_primitive, nr );
186 // fprintf(stderr,"Emit prim %d\n", rmesa->radeon.tcl.aos_count);
189 rmesa->radeon.tcl
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H A Dr200_state_init.c57 * the tcl scalar and vector areas.
264 TCL_CHECK( tcl, GL_TRUE, 0 )
709 ALLOC_STATE( tcl, tcl_or_vp, TCL_STATE_SIZE, "TCL/tcl", 0 );
710 ALLOC_STATE( msl, tcl, MSL_STATE_SIZE, "MSL/matrix-select", 0 );
711 ALLOC_STATE( tcg, tcl, TCG_STATE_SIZE, "TCG/texcoordgen", 0 );
809 rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(rmesa, R200_EMIT_TCL_LIGHT_MODEL_CTL_0);
810 rmesa->hw.tcl.cmd[TCL_CMD_1] = cmdpkt(rmesa, R200_EMIT_TCL_UCP_VERT_BLEND_CTL);
1174 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] =
1181 rmesa->hw.tcl
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/radeon/
H A Dradeon_ioctl.c75 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.tcl);
172 uint32_t *cmd = (uint32_t *)(rmesa->radeon.cmdbuf.cs->packets + rmesa->tcl.elt_cmd_start);
181 nr = rmesa->tcl.elt_used;
231 rmesa->tcl.elt_cmd_start = rmesa->radeon.cmdbuf.cs->cdw;
258 rmesa->tcl.elt_cmd_offset = rmesa->radeon.cmdbuf.cs->cdw;
259 rmesa->tcl.elt_used = min_nr;
261 retval = (GLushort *)(rmesa->radeon.cmdbuf.cs->packets + rmesa->tcl.elt_cmd_offset);
306 rmesa->ioctl.bo = rmesa->radeon.tcl.aos[0].bo;
308 (rmesa->radeon.tcl.aos[0].offset + offset * rmesa->radeon.tcl
[all...]
H A Dradeon_maos_arrays.c159 if (!rmesa->tcl.obj.buf)
161 &(rmesa->tcl.aos[nr]),
179 if (!rmesa->tcl.norm.buf)
181 &(rmesa->tcl.aos[nr]),
205 if (!rmesa->tcl.rgba.buf)
207 &(rmesa->tcl.aos[nr]),
218 if (!rmesa->tcl.spec.buf) {
221 &(rmesa->tcl.aos[nr]),
236 if (!rmesa->tcl.fog.buf)
238 &(rmesa->tcl
[all...]
H A Dradeon_maos_verts.c317 GLuint vtx = (rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] &
368 if (vtx != rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT]) {
369 RADEON_STATECHANGE( rmesa, tcl );
370 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] = vtx;
377 if (rmesa->tcl.vertex_format == setup_tab[i].vertex_format &&
378 rmesa->radeon.tcl.aos[0].bo)
381 if (rmesa->radeon.tcl.aos[0].bo)
385 &rmesa->radeon.tcl.aos[0].bo,
386 &rmesa->radeon.tcl.aos[0].offset,
398 _math_trans_4f( rmesa->tcl
[all...]
H A Dradeon_tcl.c116 #define GET_MESA_ELTS() rmesa->tcl.Elts
155 rmesa->radeon.tcl.aos_count, 0 );
157 return radeonAllocEltsOpenEnded( rmesa, rmesa->tcl.vertex_format,
158 rmesa->tcl.hw_primitive, nr );
179 rmesa->radeon.tcl.aos_count,
185 rmesa->tcl.vertex_format,
186 rmesa->tcl.hw_primitive,
204 rmesa->tcl.hw_primitive == (PRIM| \
261 if (newprim != rmesa->tcl.hw_primitive ||
264 rmesa->tcl
[all...]
H A Dradeon_state.c327 RADEON_STATECHANGE(rmesa, tcl);
328 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~RADEON_TCL_FOG_MASK;
331 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= RADEON_TCL_FOG_LINEAR;
334 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= RADEON_TCL_FOG_EXP;
337 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= RADEON_TCL_FOG_EXP2;
406 GLuint t = rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL];
433 if ( rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] != t ) {
434 RADEON_STATECHANGE(rmesa, tcl );
435 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] = t;
447 RADEON_STATECHANGE( rmesa, tcl );
[all...]
H A Dradeon_context.h313 struct radeon_state_atom tcl; member in struct:r100_hw_state
421 struct r100_tcl_info tcl; member in struct:r100_context
H A Dradeon_state_init.c52 * the tcl scalar and vector areas.
547 ALLOC_STATE( tcl, always, TCL_STATE_SIZE, "TCL/tcl", 1 );
618 rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT);
835 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] =
841 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] =
849 rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_0] =
853 rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_1] =
859 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] =
863 rmesa->hw.tcl
[all...]
H A Dradeon_dma.c504 for (i = 0; i < radeon->tcl.aos_count; i++) {
505 if (radeon->tcl.aos[i].bo) {
506 radeon_bo_unref(radeon->tcl.aos[i].bo);
507 radeon->tcl.aos[i].bo = NULL;
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/radeon/
H A Dradeon_ioctl.c74 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.tcl);
171 uint32_t *cmd = (uint32_t *)(rmesa->radeon.cmdbuf.cs->packets + rmesa->tcl.elt_cmd_start);
180 nr = rmesa->tcl.elt_used;
230 rmesa->tcl.elt_cmd_start = rmesa->radeon.cmdbuf.cs->cdw;
257 rmesa->tcl.elt_cmd_offset = rmesa->radeon.cmdbuf.cs->cdw;
258 rmesa->tcl.elt_used = min_nr;
260 retval = (GLushort *)(rmesa->radeon.cmdbuf.cs->packets + rmesa->tcl.elt_cmd_offset);
305 rmesa->ioctl.bo = rmesa->radeon.tcl.aos[0].bo;
307 (rmesa->radeon.tcl.aos[0].offset + offset * rmesa->radeon.tcl
[all...]
H A Dradeon_maos_arrays.c158 if (!rmesa->tcl.obj.buf)
160 &(rmesa->tcl.aos[nr]),
178 if (!rmesa->tcl.norm.buf)
180 &(rmesa->tcl.aos[nr]),
204 if (!rmesa->tcl.rgba.buf)
206 &(rmesa->tcl.aos[nr]),
217 if (!rmesa->tcl.spec.buf) {
220 &(rmesa->tcl.aos[nr]),
235 if (!rmesa->tcl.fog.buf)
237 &(rmesa->tcl
[all...]
H A Dradeon_maos_verts.c316 GLuint vtx = (rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] &
367 if (vtx != rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT]) {
368 RADEON_STATECHANGE( rmesa, tcl );
369 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] = vtx;
376 if (rmesa->tcl.vertex_format == setup_tab[i].vertex_format &&
377 rmesa->radeon.tcl.aos[0].bo)
380 if (rmesa->radeon.tcl.aos[0].bo)
384 &rmesa->radeon.tcl.aos[0].bo,
385 &rmesa->radeon.tcl.aos[0].offset,
397 _math_trans_4f( rmesa->tcl
[all...]
H A Dradeon_tcl.c115 #define GET_MESA_ELTS() rmesa->tcl.Elts
154 rmesa->radeon.tcl.aos_count, 0 );
156 return radeonAllocEltsOpenEnded( rmesa, rmesa->tcl.vertex_format,
157 rmesa->tcl.hw_primitive, nr );
178 rmesa->radeon.tcl.aos_count,
184 rmesa->tcl.vertex_format,
185 rmesa->tcl.hw_primitive,
203 rmesa->tcl.hw_primitive == (PRIM| \
260 if (newprim != rmesa->tcl.hw_primitive ||
263 rmesa->tcl
[all...]
H A Dradeon_state.c326 RADEON_STATECHANGE(rmesa, tcl);
327 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~RADEON_TCL_FOG_MASK;
330 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= RADEON_TCL_FOG_LINEAR;
333 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= RADEON_TCL_FOG_EXP;
336 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= RADEON_TCL_FOG_EXP2;
405 GLuint t = rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL];
432 if ( rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] != t ) {
433 RADEON_STATECHANGE(rmesa, tcl );
434 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] = t;
446 RADEON_STATECHANGE( rmesa, tcl );
[all...]
H A Dradeon_context.h313 struct radeon_state_atom tcl; member in struct:r100_hw_state
421 struct r100_tcl_info tcl; member in struct:r100_context
H A Dradeon_state_init.c51 * the tcl scalar and vector areas.
547 ALLOC_STATE( tcl, always, TCL_STATE_SIZE, "TCL/tcl", 1 );
618 rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT);
835 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] =
841 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] =
849 rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_0] =
853 rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_1] =
859 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] =
863 rmesa->hw.tcl
[all...]

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