Searched refs:tiled (Results 1 - 25 of 72) sorted by relevance

123

/xsrc/external/mit/MesaLib/dist/src/asahi/lib/
H A Dtiling.h27 void agx_detile(void *tiled, void *linear,
31 void agx_tile(void *tiled, void *linear,
H A Dtiling.c92 pixel_t *ptiled = &tiled[tile_base + y_offs + x_offs];\
114 uint32_t *tiled = _tiled; local in function:agx_detile
127 uint32_t *tiled = _tiled; local in function:agx_tile
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_sdma_copy_image.c154 struct si_texture *tiled = ssrc->surface.is_linear ? sdst : ssrc; local in function:si_sdma_v4_v5_copy_texture
155 struct si_texture *linear = tiled == ssrc ? sdst : ssrc;
156 unsigned tiled_width = DIV_ROUND_UP(tiled->buffer.b.b.width0, tiled->surface.blk_w);
157 unsigned tiled_height = DIV_ROUND_UP(tiled->buffer.b.b.height0, tiled->surface.blk_h);
160 uint64_t tiled_address = tiled == ssrc ? src_address : dst_address;
164 bool dcc = vi_dcc_enabled(tiled, 0) && is_v5;
165 assert(tiled->buffer.b.b.depth0 == 1);
181 (is_v5 ? 0 : tiled
294 struct si_texture *tiled = src_mode >= RADEON_SURF_MODE_1D ? ssrc : sdst; local in function:cik_sdma_copy_texture
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/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/lima/
H A Dlima_resource.h46 bool tiled; member in struct:lima_resource
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/lima/
H A Dlima_resource.h58 bool tiled; member in struct:lima_resource
H A Dlima_resource.c227 res->tiled = should_tile;
329 res->tiled = false;
332 res->tiled = true;
338 res->tiled = false;
347 if (res->tiled ||
356 if (res->tiled && res->levels[0].stride != stride) {
357 fprintf(stderr, "tiled imported buffer has mismatching stride: %d (BO) != %d (expected)",
362 if (!res->tiled && (res->levels[0].stride % 8)) {
367 if (!res->tiled && res->levels[0].stride < stride) {
412 if (res->tiled)
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/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
H A Dradv_formats.c635 VkFormatFeatureFlags linear = 0, tiled = 0, buffer = 0; local in function:radv_physical_device_get_format_properties
642 out_properties->optimalTilingFeatures = tiled;
650 out_properties->optimalTilingFeatures = tiled;
676 tiled |= VK_FORMAT_FEATURE_STORAGE_IMAGE_BIT;
689 tiled |= VK_FORMAT_FEATURE_DEPTH_STENCIL_ATTACHMENT_BIT;
690 tiled |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_BIT;
691 tiled |= VK_FORMAT_FEATURE_BLIT_SRC_BIT |
693 tiled |= VK_FORMAT_FEATURE_TRANSFER_SRC_BIT |
697 tiled |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_MINMAX_BIT_EXT;
701 tiled
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/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dcik_sdma.c222 struct si_texture *tiled = src_mode >= RADEON_SURF_MODE_1D ? ssrc : sdst; local in function:cik_sdma_copy_texture
223 struct si_texture *linear = tiled == ssrc ? sdst : ssrc;
224 unsigned tiled_level = tiled == ssrc ? src_level : dst_level;
226 unsigned tiled_x = tiled == ssrc ? srcx : dstx;
228 unsigned tiled_y = tiled == ssrc ? srcy : dsty;
230 unsigned tiled_z = tiled == ssrc ? srcz : dstz;
232 unsigned tiled_width = tiled == ssrc ? src_width : dst_width;
234 unsigned tiled_pitch = tiled == ssrc ? src_pitch : dst_pitch;
236 unsigned tiled_slice_pitch = tiled == ssrc ? src_slice_pitch : dst_slice_pitch;
238 uint64_t tiled_address = tiled
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H A Dsi_dma.c101 struct si_texture *tiled = detile ? ssrc : sdst; local in function:si_dma_copy_tile
105 unsigned index = tiled->surface.u.legacy.tiling_index[tiled_lvl];
127 assert(!util_format_is_depth_and_stencil(tiled->buffer.b.b.format));
130 slice_tile_max = (tiled->surface.u.legacy.level[tiled_lvl].nblk_x *
131 tiled->surface.u.legacy.level[tiled_lvl].nblk_y) / (8*8) - 1;
137 height = tiled->surface.u.legacy.level[tiled_lvl].nblk_y;
138 base = tiled->surface.u.legacy.level[tiled_lvl].offset;
146 tile_split = util_logbase2(tiled->surface.u.legacy.tile_split >> 6);
148 base += tiled->buffer.gpu_address;
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/v3d/
H A Dv3d_resource.h130 bool tiled; member in struct:v3d_resource
H A Dv3d_blit.c201 struct pipe_resource *tiled = NULL; local in function:v3d_render_blit
203 if (!src->tiled) {
221 tiled = ctx->screen->resource_create(ctx->screen, &tmpl);
222 if (!tiled) {
223 fprintf(stderr, "Failed to create tiled blit temp\n");
227 tiled, 0,
232 info->src.resource = tiled;
245 pipe_resource_reference(&tiled, NULL);
H A Dv3d_resource.c264 if (rsc->tiled) {
265 /* No direct mappings of tiled, since we need to manually
324 if (!rsc->tiled) {
329 /* Otherwise, map and store the texture data directly into the tiled
389 if (rsc->tiled) {
390 /* A shared tiled buffer should always be allocated as UIF,
526 if (!rsc->tiled) {
704 /* Use a tiled layout if we can, for better 3D performance. */
737 rsc->tiled = should_tile;
741 rsc->tiled
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/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/vc4/
H A Dvc4_resource.h58 bool tiled; member in struct:vc4_resource
H A Dvc4_resource.c184 if (rsc->tiled) {
185 /* No direct mappings of tiled, since we need to manually
249 if (!rsc->tiled ||
256 /* Otherwise, map and store the texture data directly into the tiled
306 if (rsc->tiled)
368 if (!rsc->tiled) {
468 if (!rsc->tiled) {
492 /* Use a tiled layout if we can, for better 3D performance. */
530 rsc->tiled = should_tile;
534 rsc->tiled
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/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/v3d/
H A Dv3d_resource.h96 bool tiled; member in struct:v3d_resource
H A Dv3d_resource.c294 if (rsc->tiled) {
295 /* No direct mappings of tiled, since we need to manually
354 if (!rsc->tiled) {
359 /* Otherwise, map and store the texture data directly into the tiled
402 if (rsc->tiled) {
403 /* A shared tiled buffer should always be allocated as UIF,
586 if (!rsc->tiled) {
764 /* Use a tiled layout if we can, for better 3D performance. */
797 rsc->tiled = should_tile;
801 rsc->tiled
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H A Dv3d_blit.c66 struct pipe_resource *tiled = NULL; local in function:v3d_render_blit
71 if (!src->tiled) {
89 tiled = ctx->screen->resource_create(ctx->screen, &tmpl);
90 if (!tiled) {
91 fprintf(stderr, "Failed to create tiled blit temp\n");
95 tiled, 0,
100 info->src.resource = tiled;
113 pipe_resource_reference(&tiled, NULL);
566 * the NV12 format with BROADCOM_SAND_COL128 modifier to UIF tiled format.
609 * the NV12 format with BROADCOM_SAND_COL128 modifier to UIF tiled forma
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/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/vc4/
H A Dvc4_resource.h58 bool tiled; member in struct:vc4_resource
H A Dvc4_resource.c183 if (rsc->tiled) {
184 /* No direct mappings of tiled, since we need to manually
248 if (!rsc->tiled ||
255 /* Otherwise, map and store the texture data directly into the tiled
289 if (rsc->tiled)
395 if (!rsc->tiled) {
495 if (!rsc->tiled) {
519 /* Use a tiled layout if we can, for better 3D performance. */
557 rsc->tiled = should_tile;
561 rsc->tiled
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/xsrc/external/mit/MesaLib/dist/docs/isl/
H A Dtiling.rst20 The basic idea of a tiled image is that the image is first divided into
23 demonstrated with a specific example. Suppose we have a RGBA8888 X-tiled
32 :alt: Example of an X-tiled image
35 instead, Y-tiled. Then the surface is divided into 32x32 pixel tiles each of
123 simply said it was Y-tiled but by Sky Lake there is almost no mention of
124 Y-tiling in connection with stencil buffers and they are always W-tiled. This
162 tiled address:
199 Starting with Sky Lake, we can scan out from Y-tiled buffers.
204 When bit-6 swizzling is enabled, bit 9 is XOR'd in with bit 6 of the tiled
232 the docs are somewhat confused as to whether stencil buffers are W or Y-tiled
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H A Dccs.rst44 on the main surface of 16x16 sets of 128 byte Y-tiled cache-line-pairs.
45 CCS is always Y tiled.
58 two cache lines being vertically adjacent when the main surface is X-tiled and
59 horizontally adjacent when the main surface is Y-tiled. For an X-tiled surface
60 this forms an area of 64B x 2rows and for a Y-tiled surface this forms an area
133 boundary: horizontal when the primary surface is X-tiled and vertical when
134 Y-tiled. For a 32bpp format, this works out to an alignment of 256x128 main
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_formats.c698 VkFormatFeatureFlags2KHR linear = 0, tiled = 0, buffer = 0; local in function:radv_physical_device_get_format_properties
706 out_properties->optimalTilingFeatures = tiled;
713 out_properties->optimalTilingFeatures = tiled;
739 tiled |= VK_FORMAT_FEATURE_2_STORAGE_IMAGE_BIT_KHR |
758 tiled |= VK_FORMAT_FEATURE_2_DEPTH_STENCIL_ATTACHMENT_BIT_KHR;
759 tiled |= VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_BIT_KHR;
760 tiled |= VK_FORMAT_FEATURE_2_BLIT_SRC_BIT_KHR | VK_FORMAT_FEATURE_2_BLIT_DST_BIT_KHR;
761 tiled |= VK_FORMAT_FEATURE_2_TRANSFER_SRC_BIT_KHR | VK_FORMAT_FEATURE_2_TRANSFER_DST_BIT_KHR;
764 tiled |= VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_FILTER_MINMAX_BIT_KHR;
767 tiled |
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/xsrc/external/mit/libdrm/dist/omap/
H A Domap_drm.h54 #define OMAP_BO_TILED_MASK 0x00000f00 /* tiled mapping mask, see tiled modes */
61 /* tiled modes */
68 uint32_t bytes; /* (for non-tiled formats) */
72 } tiled; /* (for tiled formats) */ member in union:omap_gem_size
108 /* note: in case of tiled buffers, the user virtual size can be
H A Domap_drm.c211 bo->size = round_up(size.tiled.width, PAGE_SIZE) * size.tiled.height;
224 /* allocate a new (un-tiled) buffer object */
243 .tiled = {
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dsna_video.h97 bool tiled; member in struct:sna_video

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