| /xsrc/external/mit/MesaLib/dist/src/amd/compiler/tests/ |
| test_optimizer_postRA.cpp | 46 /* Recognize when the result of VOPC goes to VCC, and use that for the branching then. */
48 //! s2: %b:vcc = v_cmp_eq_u32 0, %a:v[0]
49 //! s2: %e:s[2-3] = p_cbranch_z %b:vcc
51 auto vcmp = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(bld.lm, vcc), Operand::zero(),
53 auto sand = bld.sop2(Builder::s_and, bld.def(bld.lm, reg_s0), bld.def(s1, scc), bld.vcc(vcmp), Operand(exec, bld.lm));
61 /* When VCC is overwritten inbetween, don't optimize. */
63 //! s2: %b:vcc = v_cmp_eq_u32 0, %a:v[0]
64 //! s2: %c:s[0-1], s1: %d:scc = s_and_b64 %b:vcc, %x:exec
65 //! s2: %f:vcc = s_mov_b64 0
67 //! p_unit_test 1, %e:s[2-3], %f:vcc
[all...] |
| test_sdwa.cpp | 102 bld.vopc_sdwa(aco_opcode::v_cmp_gt_f32, bld.def(bld.lm, vcc), inputs[0], inputs[1]);
104 //~gfx8! SDWA+VOPC definition must be fixed to vcc on GFX8: s2: %_ = v_cmp_lt_f32 %vgpr0, %vgpr1 src0_sel:dword src1_sel:dword
107 //~gfx(9|10)! SDWA VOPC clamp only supported on GFX8: s2: %_:vcc = v_cmp_eq_f32 %vgpr0, %vgpr1 clamp src0_sel:dword src1_sel:dword
108 bld.vopc_sdwa(aco_opcode::v_cmp_eq_f32, bld.def(bld.lm, vcc), inputs[0], inputs[1]).instr->sdwa().clamp = true;
132 BEGIN_TEST(validate.sdwa.vcc)
139 //! 3rd operand must be fixed to vcc with SDWA: v1: %_ = v_cndmask_b32 %vgpr0, %vgpr1, %_ dst_sel:dword src0_sel:dword src1_sel:dword
141 bld.vop2_sdwa(aco_opcode::v_cndmask_b32, bld.def(v1), inputs[0], inputs[1], bld.vcc(inputs[2]));
143 //! 2nd definition must be fixed to vcc with SDWA: v1: %_, s2: %_ = v_add_co_u32 %vgpr0, %vgpr1 dst_sel:dword src0_sel:dword src1_sel:dword
145 bld.vop2_sdwa(aco_opcode::v_add_co_u32, bld.def(v1), bld.def(bld.lm, vcc), inputs[0], inputs[1]);
|
| /xsrc/external/mit/MesaLib/dist/src/amd/compiler/ |
| aco_ir.cpp | 107 108; /* includes VCC, which can be treated as s[106-107] on GFX10+ */
205 // TODO: return true if we know we will use vcc
237 // TODO: return true if we know we will use vcc
285 instr->definitions[0].setFixed(vcc);
287 instr->definitions[1].setFixed(vcc);
289 instr->operands[2].setFixed(vcc);
309 instr->definitions.back().physReg() != vcc)
312 if (!pre_ra && instr->operands.size() >= 3 && instr->operands[2].physReg() != vcc)
360 instr->definitions.back().setFixed(vcc);
363 instr->operands[2].setFixed(vcc);
[all...] |
| aco_live_var_analysis.cpp | 121 if ((definition.isFixed() || definition.hasHint()) && definition.physReg() == vcc)
150 if (operand.isFixed() && operand.physReg() == vcc)
192 if ((definition.isFixed() || definition.hasHint()) && definition.physReg() == vcc)
243 if (operand.isFixed() && operand.physReg() == vcc)
|
| aco_lower_to_hw_instr.cpp | 194 instr->definitions[1].setFixed(vcc);
217 bld.vop3(aco_opcode::v_add_co_u32_e64, dst[0], bld.def(bld.lm, vcc), vtmp_op[0], src1[0]);
219 bld.vop2_dpp(aco_opcode::v_add_co_u32, dst[0], bld.def(bld.lm, vcc), src0[0], src1[0],
222 bld.vop2_dpp(aco_opcode::v_addc_co_u32, dst[1], bld.def(bld.lm, vcc), src0[1], src1[1],
223 Operand(vcc, bld.lm), dpp_ctrl, row_mask, bank_mask, bound_ctrl);
258 bld.vopc(cmp, bld.def(bld.lm, vcc), vtmp_op64, src1_64);
259 bld.vop2(aco_opcode::v_cndmask_b32, dst[0], vtmp_op[0], src1[0], Operand(vcc, bld.lm));
260 bld.vop2(aco_opcode::v_cndmask_b32, dst[1], vtmp_op[1], src1[1], Operand(vcc, bld.lm));
327 bld.vop3(aco_opcode::v_add_co_u32_e64, dst[0], bld.def(bld.lm, vcc), src0[0], src1[0]);
329 bld.vop2(aco_opcode::v_add_co_u32, dst[0], bld.def(bld.lm, vcc), src0[0], src1[0])
[all...] |
| aco_optimizer_postRA.cpp | 185 * vcc = ... ; last_vcc_wr
186 * sX, scc = s_and_bXX vcc, exec ; op0_instr
187 * (...vcc and exec must not be clobbered inbetween...)
192 * vcc = ... ; last_vcc_wr
193 * s_cbranch_XX vcc ; instr modified to use vcc
205 Idx last_vcc_wr_idx = last_writer_idx(ctx, vcc, ctx.program->lane_mask);
208 * - the instructions that wrote the operand register and VCC are both found
209 * - the operand register used by the branch, and VCC were both written in the current block
210 * - EXEC hasn't been clobbered since the last VCC writ
[all...] |
| aco_validate.cpp | 163 check((instr->definitions[0].isFixed() && instr->definitions[0].physReg() == vcc) ||
165 "SDWA+VOPC definition must be fixed to vcc on GFX8", instr.get());
195 check(instr->operands[2].isFixed() && instr->operands[2].physReg() == vcc,
196 "3rd operand must be fixed to vcc with SDWA", instr.get());
199 check(instr->definitions[1].isFixed() && instr->definitions[1].physReg() == vcc,
200 "2nd definition must be fixed to vcc with SDWA", instr.get());
897 if (op.physReg() == vcc && !program->needs_vcc)
899 "Operand %d fixed to vcc but needs_vcc=false", i);
926 if (def.physReg() == vcc && !program->needs_vcc)
928 "Definition %d fixed to vcc but needs_vcc=false", i)
[all...] |
| aco_register_allocation.cpp | 1323 PhysRegInterval vcc_win = {vcc, 2};
1324 /* VCC is outside the bounds */
1863 (reg != vcc || (instr->definitions.empty() && idx == 2) ||
1864 chip >= GFX10); /* sdata can be vcc */
2773 /* some instructions need VOP3 encoding if operand/definition is not assigned to VCC */
2776 ((instr->format == Format::VOPC && !(instr->definitions[0].physReg() == vcc)) ||
2778 !(instr->operands[2].physReg() == vcc)) ||
2785 !(instr->definitions[1].physReg() == vcc)) ||
2789 !(instr->operands[2].physReg() == vcc)));
|
| aco_optimizer.cpp | 1837 instr->definitions[0].setHint(vcc);
1912 instr->definitions[0].setHint(vcc);
2038 instr->definitions[0].setHint(vcc);
2112 instr->definitions[0].setHint(vcc);
2500 new_instr->definitions[1].setHint(vcc);
2960 /* v_and(a, v_subbrev_co(0, 0, vcc)) -> v_cndmask(0, a, vcc) */
3280 instr->definitions[0].setHint(vcc);
|
| aco_insert_NOPs.cpp | 117 /* VALU writing VCC/EXEC and then a VALU reading VCCZ/EXECZ requires 5 wait states */
121 /* VALU writing VCC followed by v_div_fmas require 4 wait states */
350 /* TODO: we don't handle accessing VCC using the actual SGPR instead of using the alias */
505 if (def.physReg() == vcc || def.physReg() == vcc_hi) {
|
| aco_assembler.cpp | 703 if (instr->definitions[0].physReg() != vcc) {
|
| aco_instruction_selection.cpp | 203 return bld.pseudo(aco_opcode::p_bpermute, bld.def(v1), bld.def(bld.lm), bld.def(bld.lm, vcc),
3117 .setHint(vcc);
6765 .setHint(vcc);
7820 /* vcc clobber */
7830 defs[num_defs++] = bld.def(bld.lm, vcc);
8054 .setHint(vcc);
9651 .setHint(vcc);
10300 branch->definitions[0].setHint(vcc);
10341 branch->definitions[0].setHint(vcc);
10360 branch->definitions[0].setHint(vcc);
[all...] |
| aco_ir.h | 453 static constexpr PhysReg vcc{106};
1473 * the definition doesn't have to be VCC on GFX9+.
1679 * Definition(4): vcc clobber
|
| /xsrc/external/mit/freetype/dist/builds/windows/ |
| detect.mk | 119 CONFIG_FILE := w32-vcc.mk
|
| /xsrc/external/mit/fontconfig/dist/ |
| configure | 17942 { /* ULTRIX-32 V3.1 (Rev 9) vcc rejects this */
|
| /xsrc/external/mit/xorg-server/dist/ |
| configure | 24886 { /* ULTRIX-32 V3.1 (Rev 9) vcc rejects this */
[all...] |
| /xsrc/external/mit/xorg-server.old/dist/ |
| configure | 23020 { /* ULTRIX-32 V3.1 (Rev 9) vcc rejects this */
[all...] |
