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  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_cdclk.h 23 u8 divider; /* CD2X divider * 2 */ member in struct:intel_cdclk_vals
intel_cdclk.h 23 u8 divider; /* CD2X divider * 2 */ member in struct:intel_cdclk_vals
intel_cdclk.h 23 u8 divider; /* CD2X divider * 2 */ member in struct:intel_cdclk_vals
intel_lvds.c 64 int divider; member in struct:intel_lvds_pps
176 pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val);
201 "divider %d port %d powerdown_on_reset %d\n",
203 pps->divider, pps->port, pps->powerdown_on_reset);
227 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) |
intel_lvds.c 64 int divider; member in struct:intel_lvds_pps
176 pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val);
201 "divider %d port %d powerdown_on_reset %d\n",
203 pps->divider, pps->port, pps->powerdown_on_reset);
227 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) |
intel_lvds.c 64 int divider; member in struct:intel_lvds_pps
176 pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val);
201 "divider %d port %d powerdown_on_reset %d\n",
203 pps->divider, pps->port, pps->powerdown_on_reset);
227 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) |
  /src/sys/arch/arm/broadcom/
bcm2835_bsc.c 103 u_int divider = howmany(sc->sc_frequency, sc->sc_clkrate); local in function:bsciic_attach
105 __SHIFTIN(divider, BSC_DIV_CDIV));
bcm2835_bsc.c 103 u_int divider = howmany(sc->sc_frequency, sc->sc_clkrate); local in function:bsciic_attach
105 __SHIFTIN(divider, BSC_DIV_CDIV));
bcm2835_bsc.c 103 u_int divider = howmany(sc->sc_frequency, sc->sc_clkrate); local in function:bsciic_attach
105 __SHIFTIN(divider, BSC_DIV_CDIV));
  /src/sys/dev/marvell/
mvspi.c 157 uint32_t divider; local in function:mvspi_configure
196 divider = spr * (1 << sppr);
198 if ((mvTclk / divider) > speed)
202 if ((mvTclk / divider) == speed) {
210 if ((speed - (mvTclk / divider)) < min_baud_offset) {
211 min_baud_offset = (speed - (mvTclk / divider));
mvspi.c 157 uint32_t divider; local in function:mvspi_configure
196 divider = spr * (1 << sppr);
198 if ((mvTclk / divider) > speed)
202 if ((mvTclk / divider) == speed) {
210 if ((speed - (mvTclk / divider)) < min_baud_offset) {
211 min_baud_offset = (speed - (mvTclk / divider));
mvspi.c 157 uint32_t divider; local in function:mvspi_configure
196 divider = spr * (1 << sppr);
198 if ((mvTclk / divider) > speed)
202 if ((mvTclk / divider) == speed) {
210 if ((speed - (mvTclk / divider)) < min_baud_offset) {
211 min_baud_offset = (speed - (mvTclk / divider));
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/clk/
nouveau_nvkm_subdev_clk_gk20a.c 97 u32 divider; local in function:gk20a_pllg_calc_rate
100 divider = pll->m * clk->pl_to_div(pll->pl);
102 return rate / divider / 2;
310 /* split VCO-to-bypass jump in half by setting out divider 1:2 */
313 /* Intentional 2nd write to assure linear divider operation */
327 /* restore out divider 1:1 */
331 /* Intentional 2nd write to assure linear divider operation */
nouveau_nvkm_subdev_clk_gk20a.c 97 u32 divider; local in function:gk20a_pllg_calc_rate
100 divider = pll->m * clk->pl_to_div(pll->pl);
102 return rate / divider / 2;
310 /* split VCO-to-bypass jump in half by setting out divider 1:2 */
313 /* Intentional 2nd write to assure linear divider operation */
327 /* restore out divider 1:1 */
331 /* Intentional 2nd write to assure linear divider operation */
nouveau_nvkm_subdev_clk_gk20a.c 97 u32 divider; local in function:gk20a_pllg_calc_rate
100 divider = pll->m * clk->pl_to_div(pll->pl);
102 return rate / divider / 2;
310 /* split VCO-to-bypass jump in half by setting out divider 1:2 */
313 /* Intentional 2nd write to assure linear divider operation */
327 /* restore out divider 1:1 */
331 /* Intentional 2nd write to assure linear divider operation */
  /src/sys/arch/arm/nxp/
imx6_ccm.c 425 u_int divider = uimax(1, rate_parent / rate); local in function:imxccm_clk_set_rate_div
440 if (div->tbl[i] == divider)
448 v |= __SHIFTIN(divider - 1, div->mask);
imx6_ccm.c 425 u_int divider = uimax(1, rate_parent / rate); local in function:imxccm_clk_set_rate_div
440 if (div->tbl[i] == divider)
448 v |= __SHIFTIN(divider - 1, div->mask);
imx6_ccm.c 425 u_int divider = uimax(1, rate_parent / rate); local in function:imxccm_clk_set_rate_div
440 if (div->tbl[i] == divider)
448 v |= __SHIFTIN(divider - 1, div->mask);
  /src/sys/dev/i2c/
sensirion_voc_algorithm.c 136 uint32_t divider = (uint32_t)((b >= 0) ? b : (-b)); local in function:fix16_div
142 while (divider < remainder) {
143 divider <<= 1;
152 if (divider & 0x80000000) {
154 // We know that divider's bottom bit is 0 here.
155 if (remainder >= divider) {
157 remainder -= divider;
159 divider >>= 1;
165 if (remainder >= divider) {
167 remainder -= divider;
    [all...]
sensirion_voc_algorithm.c 136 uint32_t divider = (uint32_t)((b >= 0) ? b : (-b)); local in function:fix16_div
142 while (divider < remainder) {
143 divider <<= 1;
152 if (divider & 0x80000000) {
154 // We know that divider's bottom bit is 0 here.
155 if (remainder >= divider) {
157 remainder -= divider;
159 divider >>= 1;
165 if (remainder >= divider) {
167 remainder -= divider;
    [all...]
sensirion_voc_algorithm.c 136 uint32_t divider = (uint32_t)((b >= 0) ? b : (-b)); local in function:fix16_div
142 while (divider < remainder) {
143 divider <<= 1;
152 if (divider & 0x80000000) {
154 // We know that divider's bottom bit is 0 here.
155 if (remainder >= divider) {
157 remainder -= divider;
159 divider >>= 1;
165 if (remainder >= divider) {
167 remainder -= divider;
    [all...]
  /src/sys/dev/pci/
cmpci.c 303 int divider; member in struct:__anon3999e0510108
332 return cmpci_rate_table[index].divider;
598 DPRINTF(("%s: sample:%u, divider=%d\n",
cmpci.c 303 int divider; member in struct:__anon3999e0510108
332 return cmpci_rate_table[index].divider;
598 DPRINTF(("%s: sample:%u, divider=%d\n",
cmpci.c 303 int divider; member in struct:__anon3999e0510108
332 return cmpci_rate_table[index].divider;
598 DPRINTF(("%s: sample:%u, divider=%d\n",
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_legacy_crtc.c 770 int divider; member in struct:radeon_set_pll::__anond72bf03f0108
838 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
839 if (post_div->divider == post_divider)
843 if (!post_div->divider)
945 This appears to related to the PLL divider registers (fail to lock?).
991 /* R300 uses ref_div_acc field as real ref divider */

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