| /xsrc/external/mit/MesaLib/dist/src/panfrost/bifrost/ |
| H A D | bi_lower_divergent_indirects.c | 89 nir_ssa_def *lane = nir_load_subgroup_invocation(b); local in function:bi_lower_divergent_indirects_impl
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| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| H A D | intel_dp_link_training.c | 48 int lane; local in function:intel_get_adjust_train
124 int lane; local in function:intel_dp_link_max_vswing_reached
[all...] |
| H A D | intel_dpio_phy.c | 602 int lane; local in function:bxt_ddi_phy_set_lane_optim_mask
628 int lane; local in function:bxt_ddi_phy_get_lane_lat_optim_mask
[all...] |
| H A D | icl_dsi.c | 213 int lane; local in function:dsi_program_swing_and_deemphasis
398 int lane; local in function:gen11_dsi_config_phy_lanes_sequence
[all...] |
| /src/sys/external/isc/libsodium/dist/src/libsodium/crypto_pwhash/argon2/ |
| H A D | argon2-core.h | 115 uint32_t lane; member in struct:Argon2_position_t
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| /src/sys/arch/arm/rockchip/ |
| H A D | rk3399_pcie_phy.c | 120 uint8_t * const lane = priv; local in function:rkpciephy_phy_enable
202 rkpcie_phy_poweron(struct rkpciephy_softc *sc, u_int lane) argument
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| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/codegen/ |
| H A D | nv50_ir_lowering_gm107.cpp | 122 Value *lane = bld.mkImm(l); local in function:nv50_ir::GM107LoweringPass::handleManualTXD
[all...] |
| H A D | nv50_ir_emit_nv50.cpp | 834 CodeEmitterNV50::emitQUADOP(const Instruction *i, uint8_t lane, uint8_t quOp) argument
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| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/codegen/ |
| H A D | nv50_ir_lowering_gm107.cpp | 141 Value *lane = bld.mkImm(l); local in function:nv50_ir::GM107LoweringPass::handleManualTXD
[all...] |
| H A D | nv50_ir_emit_nv50.cpp | 841 CodeEmitterNV50::emitQUADOP(const Instruction *i, uint8_t lane, uint8_t quOp) argument
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| /xsrc/external/mit/MesaLib/src/panfrost/bifrost/ |
| H A D | bi_printer.c | 245 bi_lane_as_str(enum bi_lane lane) argument
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| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/swr/rasterizer/jitter/ |
| H A D | builder_mem.cpp | 480 uint32_t lane = ((i == 0) || (i == 2)) ? 0 : 1; local in function:SwrJit::Builder::Shuffle16bpcGather4
580 uint32_t lane = ((i == 0) || (i == 2)) ? 0 : 1; local in function:SwrJit::Builder::Shuffle8bpcGather4
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/disp/ |
| H A D | nouveau_nvkm_engine_disp_dp.c | 93 u8 lane = (lt->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf; local in function:nvkm_dp_train_drive
180 u8 lane = (lt->stat[i >> 1] >> ((i & 1) * 4)) & 0xf; local in function:nvkm_dp_train_eq
208 u8 lane = (lt->stat[i >> 1] >> ((i & 1) * 4)) & 0xf; local in function:nvkm_dp_train_cr
494 u8 lane = (stat[i >> 1] >> ((i & 1) * 4)) & 0x0f; local in function:nvkm_dp_acquire
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| H A D | radeon_atombios_dp.c | 275 int lane; local in function:dp_get_adjust_train
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| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_atombios_dp.c | 217 int lane; local in function:amdgpu_atombios_dp_get_adjust_train
[all...] |
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/swr/rasterizer/jitter/ |
| H A D | builder_mem.cpp | 475 uint32_t lane = ((i == 0) || (i == 2)) ? 0 : 1; local in function:SwrJit::Builder::Shuffle16bpcGather4
575 uint32_t lane = ((i == 0) || (i == 2)) ? 0 : 1; local in function:SwrJit::Builder::Shuffle8bpcGather4
[all...] |
| H A D | fetch_jit.cpp | 391 for (uint32_t lane = 0; lane < mVWidth; ++lane) local in function:FetchJit::CreateGatherOddFormats
1115 for (int64_t lane local in function:FetchJit::GetSimdValidIndicesHelper
1333 uint32_t lane = ((i == 0) || (i == 2)) ? 0 : 1; local in function:FetchJit::Shuffle8bpcGatherd16
1703 uint32_t lane = ((i == 0) || (i == 2)) ? 0 : 1; local in function:FetchJit::Shuffle16bpcGather16
1949 uint32_t lane = ((i == 0) || (i == 2)) ? 0 : 1; local in function:FetchJit::Shuffle16bpcGather
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/ |
| H A D | drm_dp_helper.c | 75 int lane; local in function:drm_dp_channel_eq_ok
93 int lane; local in function:drm_dp_clock_recovery_ok
61 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE],int lane) argument
105 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],int lane) argument
118 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],int lane) argument
138 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZE],unsigned int lane) argument
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| H A D | amdgpu_dce_link_encoder.c | 1119 int32_t lane = 0; local in function:dce110_link_encoder_dp_set_lane_settings
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| H A D | amdgpu_dcn10_link_encoder.c | 1085 int32_t lane = 0; local in function:dcn10_link_encoder_dp_set_lane_settings
[all...] |
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/swr/rasterizer/core/core/ |
| H A D | pa_avx.cpp | 157 INLINE simd4scalar swizzleLaneN(const simdvector& v, int lane) argument
311 INLINE simd4scalar swizzleLaneN(const simd16vector& v, int lane) argument
505 for (uint32_t lane = 0; lane < KNOB_SIMD_WIDTH; ++lane) local in function:PaPatchListTerm
564 for (uint32_t lane = 0; lane < KNOB_SIMD16_WIDTH; ++lane) local in function:PaPatchListTerm_simd16
1820 const int lane = pa.numPrims - pa.numPrimsComplete - 1; local in function:PaLineLoop1
1872 const int lane = pa.numPrims - pa.numPrimsComplete - 1; local in function:PaLineLoop1_simd16
[all...] |
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/docs/source/ |
| H A D | tgsi.rst | |
| /xsrc/external/mit/MesaLib/dist/docs/gallium/ |
| H A D | tgsi.rst | |
| /src/sys/arch/arm/nvidia/ |
| H A D | tegra210_xusbpad.c | 663 tegra210_xusbpad_find_func(const struct tegra210_xusbpad_lane *lane, argument
685 const struct tegra210_xusbpad_lane *lane; local in function:tegra210_xusbpad_configure_lane
[all...] |
| /xsrc/external/mit/xf86-video-ati/dist/src/ |
| H A D | atombios_output.c | 2414 static uint8_t dp_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane) argument
2424 int lane; local in function:dp_clock_recovery_ok
2446 int lane; local in function:dp_channel_eq_ok
2483 dp_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],int lane) argument
2497 dp_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],int lane) argument
2561 int lane; local in function:dp_get_adjust_train
[all...] |