| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| r100_track.h | 46 unsigned num_levels; member in struct:r100_cs_track_texture
|
| r100_track.h | 46 unsigned num_levels; member in struct:r100_cs_track_texture
|
| trinity_dpm.h | 50 u32 num_levels; member in struct:trinity_ps
|
| trinity_dpm.h | 50 u32 num_levels; member in struct:trinity_ps
|
| kv_dpm.h | 85 u32 num_levels; member in struct:kv_ps
|
| sumo_dpm.h | 49 u32 num_levels; member in struct:sumo_ps
|
| kv_dpm.h | 85 u32 num_levels; member in struct:kv_ps
|
| sumo_dpm.h | 49 u32 num_levels; member in struct:sumo_ps
|
| radeon_si_dpm.c | 3900 u32 data, num_bits, num_levels; local in function:si_validate_phase_shedding_tables
3912 num_levels = (1 << num_bits);
3914 if (table->count != num_levels)
3917 if (limits->count != (num_levels - 1))
|
| radeon_si_dpm.c | 3900 u32 data, num_bits, num_levels; local in function:si_validate_phase_shedding_tables
3912 num_levels = (1 << num_bits);
3914 if (table->count != num_levels)
3917 if (limits->count != (num_levels - 1))
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/ |
| dm_pp_interface.h | 177 uint32_t num_levels; member in struct:pp_clock_levels_with_latency
187 uint32_t num_levels; member in struct:pp_clock_levels_with_voltage
|
| dm_pp_interface.h | 177 uint32_t num_levels; member in struct:pp_clock_levels_with_latency
187 uint32_t num_levels; member in struct:pp_clock_levels_with_voltage
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| kv_dpm.h | 111 u32 num_levels; member in struct:kv_ps
|
| kv_dpm.h | 111 u32 num_levels; member in struct:kv_ps
|
| amdgpu_si_dpm.c | 4364 u32 data, num_bits, num_levels; local in function:si_validate_phase_shedding_tables
4376 num_levels = (1 << num_bits);
4378 if (table->count != num_levels)
4381 if (limits->count != (num_levels - 1))
|
| amdgpu_si_dpm.c | 4364 u32 data, num_bits, num_levels; local in function:si_validate_phase_shedding_tables
4376 num_levels = (1 << num_bits);
4378 if (table->count != num_levels)
4381 if (limits->count != (num_levels - 1))
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| dm_services_types.h | 100 uint32_t num_levels; member in struct:dm_pp_clock_levels
110 uint32_t num_levels; member in struct:dm_pp_clock_levels_with_latency
120 uint32_t num_levels; member in struct:dm_pp_clock_levels_with_voltage
|
| dm_services_types.h | 100 uint32_t num_levels; member in struct:dm_pp_clock_levels
110 uint32_t num_levels; member in struct:dm_pp_clock_levels_with_latency
120 uint32_t num_levels; member in struct:dm_pp_clock_levels_with_voltage
|
| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_debugfs.c | 3230 int num_levels; local in function:wm_latency_show
3233 num_levels = 3;
3235 num_levels = 1;
3237 num_levels = 3;
3239 num_levels = ilk_wm_max_level(dev_priv) + 1;
3243 for (level = 0; level < num_levels; level++) {
3347 int num_levels; local in function:wm_latency_write
3353 num_levels = 3;
3355 num_levels = 1;
3357 num_levels = 3
[all...] |
| intel_pm.c | 1226 int num_levels = intel_wm_num_levels(to_i915(plane->base.dev)); local in function:g4x_raw_plane_wm_compute
1238 for (level = 0; level < num_levels; level++) {
1790 int num_levels = intel_wm_num_levels(dev_priv); local in function:vlv_raw_plane_wm_set
1793 for (; level < num_levels; level++) {
1809 int num_levels = intel_wm_num_levels(to_i915(plane->base.dev)); local in function:vlv_raw_plane_wm_compute
1818 for (level = 0; level < num_levels; level++) {
1924 wm_state->num_levels = intel_wm_num_levels(dev_priv);
1932 for (level = 0; level < wm_state->num_levels; level++) {
1960 wm_state->num_levels = level;
2088 intermediate->num_levels = min(optimal->num_levels, active->num_levels)
[all...] |
| i915_debugfs.c | 3230 int num_levels; local in function:wm_latency_show
3233 num_levels = 3;
3235 num_levels = 1;
3237 num_levels = 3;
3239 num_levels = ilk_wm_max_level(dev_priv) + 1;
3243 for (level = 0; level < num_levels; level++) {
3347 int num_levels; local in function:wm_latency_write
3353 num_levels = 3;
3355 num_levels = 1;
3357 num_levels = 3
[all...] |
| intel_pm.c | 1226 int num_levels = intel_wm_num_levels(to_i915(plane->base.dev)); local in function:g4x_raw_plane_wm_compute
1238 for (level = 0; level < num_levels; level++) {
1790 int num_levels = intel_wm_num_levels(dev_priv); local in function:vlv_raw_plane_wm_set
1793 for (; level < num_levels; level++) {
1809 int num_levels = intel_wm_num_levels(to_i915(plane->base.dev)); local in function:vlv_raw_plane_wm_compute
1818 for (level = 0; level < num_levels; level++) {
1924 wm_state->num_levels = intel_wm_num_levels(dev_priv);
1932 for (level = 0; level < wm_state->num_levels; level++) {
1960 wm_state->num_levels = level;
2088 intermediate->num_levels = min(optimal->num_levels, active->num_levels)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_display_types.h | 694 u8 num_levels; member in struct:vlv_wm_state
|
| intel_display_types.h | 694 u8 num_levels; member in struct:vlv_wm_state
|
