| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_pipe_crc.c | 295 struct intel_crtc_state *pipe_config; local
311 pipe_config = intel_atomic_get_crtc_state(state, crtc);
312 if (IS_ERR(pipe_config)) {
313 ret = PTR_ERR(pipe_config);
317 pipe_config->uapi.mode_changed = pipe_config->has_psr;
318 pipe_config->crc_enabled = enable;
321 pipe_config->hw.active && crtc->pipe == PIPE_A &&
322 pipe_config->cpu_transcoder == TRANSCODER_EDP)
323 pipe_config->uapi.mode_changed = true
[all...] |
| intel_pipe_crc.c | 295 struct intel_crtc_state *pipe_config; local
311 pipe_config = intel_atomic_get_crtc_state(state, crtc);
312 if (IS_ERR(pipe_config)) {
313 ret = PTR_ERR(pipe_config);
317 pipe_config->uapi.mode_changed = pipe_config->has_psr;
318 pipe_config->crc_enabled = enable;
321 pipe_config->hw.active && crtc->pipe == PIPE_A &&
322 pipe_config->cpu_transcoder == TRANSCODER_EDP)
323 pipe_config->uapi.mode_changed = true
[all...] |
| intel_overlay.c | 937 const struct intel_crtc_state *pipe_config = local
940 if (rec->dst_x < pipe_config->pipe_src_w &&
941 rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w &&
942 rec->dst_y < pipe_config->pipe_src_h &&
943 rec->dst_y + rec->dst_height <= pipe_config->pipe_src_h)
|
| intel_overlay.c | 937 const struct intel_crtc_state *pipe_config = local
940 if (rec->dst_x < pipe_config->pipe_src_w &&
941 rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w &&
942 rec->dst_y < pipe_config->pipe_src_h &&
943 rec->dst_y + rec->dst_height <= pipe_config->pipe_src_h)
|
| intel_display.c | 157 struct intel_crtc_state *pipe_config);
159 struct intel_crtc_state *pipe_config);
174 const struct intel_crtc_state *pipe_config);
176 const struct intel_crtc_state *pipe_config);
252 const struct intel_crtc_state *pipe_config)
255 return pipe_config->port_clock; /* SPLL */
1399 const struct intel_crtc_state *pipe_config)
1404 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1413 const struct intel_crtc_state *pipe_config)
1418 assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder)
8434 struct intel_crtc_state *pipe_config; local
13978 struct intel_crtc_state *pipe_config = old_crtc_state; local
[all...] |
| intel_display.c | 157 struct intel_crtc_state *pipe_config);
159 struct intel_crtc_state *pipe_config);
174 const struct intel_crtc_state *pipe_config);
176 const struct intel_crtc_state *pipe_config);
252 const struct intel_crtc_state *pipe_config)
255 return pipe_config->port_clock; /* SPLL */
1399 const struct intel_crtc_state *pipe_config)
1404 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1413 const struct intel_crtc_state *pipe_config)
1418 assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder)
8434 struct intel_crtc_state *pipe_config; local
13978 struct intel_crtc_state *pipe_config = old_crtc_state; local
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_atombios_crtc.c | 1363 u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f; local
1365 fb_format |= CIK_GRPH_PIPE_CONFIG(pipe_config);
|
| radeon_atombios_crtc.c | 1363 u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f; local
1365 fb_format |= CIK_GRPH_PIPE_CONFIG(pipe_config);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_dce_v10_0.c | 1865 u32 pipe_config; local
1903 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2019 pipe_config);
|
| amdgpu_dce_v11_0.c | 1907 u32 pipe_config; local
1945 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2061 pipe_config);
|
| amdgpu_dce_v6_0.c | 1823 uint32_t fb_format, fb_pitch_pixels, pipe_config; local
1961 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1962 fb_format |= GRPH_PIPE_CONFIG(pipe_config);
|
| amdgpu_dce_v8_0.c | 1794 u32 pipe_config; local
1832 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1934 fb_format |= (pipe_config << GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT);
|
| amdgpu_dce_v10_0.c | 1865 u32 pipe_config; local
1903 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2019 pipe_config);
|
| amdgpu_dce_v11_0.c | 1907 u32 pipe_config; local
1945 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2061 pipe_config);
|
| amdgpu_dce_v6_0.c | 1823 uint32_t fb_format, fb_pitch_pixels, pipe_config; local
1961 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1962 fb_format |= GRPH_PIPE_CONFIG(pipe_config);
|
| amdgpu_dce_v8_0.c | 1794 u32 pipe_config; local
1832 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1934 fb_format |= (pipe_config << GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| dc_hw_types.h | 334 unsigned int pipe_config; member in struct:dc_tiling_info::__anon4574
|
| dc_hw_types.h | 334 unsigned int pipe_config; member in struct:dc_tiling_info::__anon4574
|
