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    Searched defs:pll (Results 1 - 25 of 98) sorted by relevancy

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  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/clk/
gt215.h 10 u32 pll; member in struct:gt215_clk_info
gt215.h 10 u32 pll; member in struct:gt215_clk_info
nouveau_nvkm_subdev_clk_nv40.c 31 #include "pll.h"
34 #include <subdev/bios/pll.h>
133 struct nvbios_pll pll; local in function:nv40_clk_calc_pll
136 ret = nvbios_pll_parse(subdev->device->bios, reg, &pll);
140 if (khz < pll.vco1.max_freq)
141 pll.vco2.max_freq = 0;
143 ret = nv04_pll_calc(subdev, &pll, khz, N1, M1, N2, M2, log2P);
173 /* use the second pll for shader/rop clock, if it differs from core */
nouveau_nvkm_subdev_clk_nv40.c 31 #include "pll.h"
34 #include <subdev/bios/pll.h>
133 struct nvbios_pll pll; local in function:nv40_clk_calc_pll
136 ret = nvbios_pll_parse(subdev->device->bios, reg, &pll);
140 if (khz < pll.vco1.max_freq)
141 pll.vco2.max_freq = 0;
143 ret = nv04_pll_calc(subdev, &pll, khz, N1, M1, N2, M2, log2P);
173 /* use the second pll for shader/rop clock, if it differs from core */
  /src/sys/arch/arm/nxp/
imx_ccm_pll.c 48 struct imx_ccm_pll *pll = &clk->u.pll; local in function:imx_ccm_pll_enable
53 if ((pll->flags & IMX_PLL_ENET) != 0)
58 val = CCM_READ(sc, clk->regidx, pll->reg);
63 CCM_WRITE(sc, clk->regidx, pll->reg, val);
72 struct imx_ccm_pll *pll= &clk->u.pll; local in function:imx_ccm_pll_get_rate
86 if ((pll->flags & IMX_PLL_ENET) != 0) {
87 /* For ENET PLL, div_mask contains the fixed output rate */
88 return pll->div_mask
109 struct imx_ccm_pll *pll = &clk->u.pll; local in function:imx_ccm_pll_get_parent
    [all...]
imx_ccm_pll.c 48 struct imx_ccm_pll *pll = &clk->u.pll; local in function:imx_ccm_pll_enable
53 if ((pll->flags & IMX_PLL_ENET) != 0)
58 val = CCM_READ(sc, clk->regidx, pll->reg);
63 CCM_WRITE(sc, clk->regidx, pll->reg, val);
72 struct imx_ccm_pll *pll= &clk->u.pll; local in function:imx_ccm_pll_get_rate
86 if ((pll->flags & IMX_PLL_ENET) != 0) {
87 /* For ENET PLL, div_mask contains the fixed output rate */
88 return pll->div_mask
109 struct imx_ccm_pll *pll = &clk->u.pll; local in function:imx_ccm_pll_get_parent
    [all...]
  /src/sys/external/gpl2/dts/dist/arch/mips/boot/dts/qca/
ar9132.dtsi 17 clocks = <&pll ATH79_CLK_CPU>;
64 clocks = <&pll ATH79_CLK_AHB>;
89 pll: pll-controller@18050000 { label
90 compatible = "qca,ar9132-pll",
91 "qca,ar9130-pll";
107 clocks = <&pll ATH79_CLK_AHB>;
151 clocks = <&pll ATH79_CLK_AHB>;
ar9132.dtsi 17 clocks = <&pll ATH79_CLK_CPU>;
64 clocks = <&pll ATH79_CLK_AHB>;
89 pll: pll-controller@18050000 { label
90 compatible = "qca,ar9132-pll",
91 "qca,ar9130-pll";
107 clocks = <&pll ATH79_CLK_AHB>;
151 clocks = <&pll ATH79_CLK_AHB>;
ar9331.dtsi 17 clocks = <&pll ATH79_CLK_CPU>;
90 pll: pll-controller@18050000 { label
91 compatible = "qca,ar9330-pll";
126 clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
141 clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
281 clocks = <&pll ATH79_CLK_AHB>;
ar9331.dtsi 17 clocks = <&pll ATH79_CLK_CPU>;
90 pll: pll-controller@18050000 { label
91 compatible = "qca,ar9330-pll";
126 clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
141 clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
281 clocks = <&pll ATH79_CLK_AHB>;
  /src/sys/arch/arm/amlogic/
meson_clk_pll.c 43 struct meson_clk_pll *pll = &clk->u.pll; local in function:meson_clk_pll_get_rate
62 val = CLK_READ(sc, pll->n.reg);
63 n = __SHIFTOUT(val, pll->n.mask);
65 val = CLK_READ(sc, pll->m.reg);
66 m = __SHIFTOUT(val, pll->m.mask);
68 if (pll->frac.mask) {
69 val = CLK_READ(sc, pll->frac.reg);
70 frac = __SHIFTOUT(val, pll->frac.mask);
80 rate += howmany(frac_rate, __SHIFTOUT_MASK(pll->frac.mask) + 1)
102 struct meson_clk_pll *pll = &clk->u.pll; local in function:meson_clk_pll_set_rate
177 struct meson_clk_pll *pll = &clk->u.pll; local in function:meson_clk_pll_get_parent
    [all...]
meson_clk_pll.c 43 struct meson_clk_pll *pll = &clk->u.pll; local in function:meson_clk_pll_get_rate
62 val = CLK_READ(sc, pll->n.reg);
63 n = __SHIFTOUT(val, pll->n.mask);
65 val = CLK_READ(sc, pll->m.reg);
66 m = __SHIFTOUT(val, pll->m.mask);
68 if (pll->frac.mask) {
69 val = CLK_READ(sc, pll->frac.reg);
70 frac = __SHIFTOUT(val, pll->frac.mask);
80 rate += howmany(frac_rate, __SHIFTOUT_MASK(pll->frac.mask) + 1)
102 struct meson_clk_pll *pll = &clk->u.pll; local in function:meson_clk_pll_set_rate
177 struct meson_clk_pll *pll = &clk->u.pll; local in function:meson_clk_pll_get_parent
    [all...]
  /src/sys/dev/i2c/
tvpll.c 47 const struct tvpll_data * pll; member in struct:tvpll
63 tvpll->pll = p;
65 if (tvpll->pll->initdata) {
68 &tvpll->pll->initdata[1], tvpll->pll->initdata[0],
73 device_printf(parent, "tvpll: %s\n", tvpll->pll->name);
88 const struct tvpll_data *pll; local in function:tvpll_algo
92 pll = tvpll->pll;
95 (p->frequency < pll->min || p->frequency > pll->max)
    [all...]
tvpll.c 47 const struct tvpll_data * pll; member in struct:tvpll
63 tvpll->pll = p;
65 if (tvpll->pll->initdata) {
68 &tvpll->pll->initdata[1], tvpll->pll->initdata[0],
73 device_printf(parent, "tvpll: %s\n", tvpll->pll->name);
88 const struct tvpll_data *pll; local in function:tvpll_algo
92 pll = tvpll->pll;
95 (p->frequency < pll->min || p->frequency > pll->max)
    [all...]
  /src/sys/arch/mips/atheros/
ar9344.c 124 uint32_t pll; local in function:ar9344_get_freqs
137 * Let's figure out the CPU PLL frequency.
139 pll = GETPLLREG(ARCHIP_PLL_CPU_PLL_CONFIG);
140 out_div = __SHIFTOUT(pll, AR9344_CPU_PLL_CONFIG_OUTDIV);
141 ref_div = __SHIFTOUT(pll, AR9344_CPU_PLL_CONFIG_REFDIV);
142 nint = __SHIFTOUT(pll, AR9344_CPU_PLL_CONFIG_NINT);
143 //nfrac = __SHIFTOUT(pll, AR9344_CPU_PLL_CONFIG_NFRAC);
148 * Now figure out the DDR PLL frequency.
150 pll = GETPLLREG(ARCHIP_PLL_DDR_PLL_CONFIG);
151 out_div = __SHIFTOUT(pll, AR9344_DDR_PLL_CONFIG_OUTDIV)
    [all...]
ar7100.c 152 const uint32_t pll = GETPLLREG(ARCHIP_PLL_CPU_PLL_CONFIG); local in function:ar7100_get_freqs
156 ref_freq * (__SHIFTOUT(pll, AR7100_PLL_PLL_FB) + 1);
159 pll_freq / (__SHIFTOUT(pll, AR7100_CPU_PLL_CPU_DIV_SEL) + 1);
162 pll_freq / (__SHIFTOUT(pll, AR7100_CPU_PLL_DDR_DIV_SEL) + 1);
165 cpu_freq / ((__SHIFTOUT(pll, AR7100_CPU_PLL_AHB_DIV) + 1) * 2);
ar9344.c 124 uint32_t pll; local in function:ar9344_get_freqs
137 * Let's figure out the CPU PLL frequency.
139 pll = GETPLLREG(ARCHIP_PLL_CPU_PLL_CONFIG);
140 out_div = __SHIFTOUT(pll, AR9344_CPU_PLL_CONFIG_OUTDIV);
141 ref_div = __SHIFTOUT(pll, AR9344_CPU_PLL_CONFIG_REFDIV);
142 nint = __SHIFTOUT(pll, AR9344_CPU_PLL_CONFIG_NINT);
143 //nfrac = __SHIFTOUT(pll, AR9344_CPU_PLL_CONFIG_NFRAC);
148 * Now figure out the DDR PLL frequency.
150 pll = GETPLLREG(ARCHIP_PLL_DDR_PLL_CONFIG);
151 out_div = __SHIFTOUT(pll, AR9344_DDR_PLL_CONFIG_OUTDIV)
    [all...]
ar7100.c 152 const uint32_t pll = GETPLLREG(ARCHIP_PLL_CPU_PLL_CONFIG); local in function:ar7100_get_freqs
156 ref_freq * (__SHIFTOUT(pll, AR7100_PLL_PLL_FB) + 1);
159 pll_freq / (__SHIFTOUT(pll, AR7100_CPU_PLL_CPU_DIV_SEL) + 1);
162 pll_freq / (__SHIFTOUT(pll, AR7100_CPU_PLL_DDR_DIV_SEL) + 1);
165 cpu_freq / ((__SHIFTOUT(pll, AR7100_CPU_PLL_AHB_DIV) + 1) * 2);
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/fb/
nouveau_nvkm_subdev_fb_ramnv40.c 34 #include <subdev/bios/pll.h>
35 #include <subdev/clk/pll.h>
44 struct nvbios_pll pll; local in function:nv40_ram_calc
48 ret = nvbios_pll_parse(bios, 0x04, &pll);
50 nvkm_error(subdev, "mclk pll data not found\n");
54 ret = nv04_pll_calc(subdev, &pll, freq, &N1, &M1, &N2, &M2, &log2P);
59 ram->ctrl |= min(pll.bias_p + log2P, (int)pll.max_p) << 20;
127 /* change the PLL of each memory partition */
nouveau_nvkm_subdev_fb_ramnv40.c 34 #include <subdev/bios/pll.h>
35 #include <subdev/clk/pll.h>
44 struct nvbios_pll pll; local in function:nv40_ram_calc
48 ret = nvbios_pll_parse(bios, 0x04, &pll);
50 nvkm_error(subdev, "mclk pll data not found\n");
54 ret = nv04_pll_calc(subdev, &pll, freq, &N1, &M1, &N2, &M2, &log2P);
59 ram->ctrl |= min(pll.bias_p + log2P, (int)pll.max_p) << 20;
127 /* change the PLL of each memory partition */
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/sprd/
sharkl3.dtsi 74 pll: pll { label in label:soc.anlg_phy_g2_regs
75 compatible = "sprd,sc9863a-pll";
sharkl3.dtsi 74 pll: pll { label in label:soc.anlg_phy_g2_regs
75 compatible = "sprd,sc9863a-pll";
  /src/sys/arch/arm/samsung/
exynos_clock.h 76 struct exynos_pll_clk pll; member in union:exynos_clk::__anoncaafd60b010a
exynos_clock.h 76 struct exynos_pll_clk pll; member in union:exynos_clk::__anoncaafd60b010a
  /src/sys/arch/arm/nvidia/
tegra_clock.h 82 struct tegra_pll_clk pll; member in union:tegra_clk::__anon56bd0515010a

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