| /src/external/gpl3/binutils/dist/opcodes/ |
| sparc-dis.c | 992 unsigned long prev_insn; local
1002 prev_insn = getword (buffer);
1014 if (is_delayed_branch (prev_insn))
1022 prev_insn = getword (buffer);
1031 if ((prev_insn & 0xc1c00000) == 0x01000000
1032 && X_RD (prev_insn) == X_RS1 (insn))
1035 info->target = (unsigned) X_IMM22 (prev_insn) << 10;
|
| aarch64-opc.c | 5849 const struct aarch64_inst *prev_insn;
5854 prev_insn = insn_sequence->instr + (insn_sequence->num_added_insns - 1);
5856 prev_insn = NULL;
5858 if (prev_insn
5859 && (prev_insn->opcode->constraints & C_SCAN_MOPS_PME)
5860 && prev_insn->opcode != opcode - 1)
5865 mismatch_detail->data[0].s = prev_insn->opcode[1].name;
5866 mismatch_detail->data[1].s = prev_insn->opcode->name;
5873 if (is_new_section || !prev_insn || prev_insn->opcode != opcode - 1
5845 const struct aarch64_inst *prev_insn; local
[all...] |
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| sparc-dis.c | 1020 unsigned long prev_insn; local
1030 prev_insn = getword (buffer);
1042 if (is_delayed_branch (prev_insn))
1050 prev_insn = getword (buffer);
1059 if ((prev_insn & 0xc1c00000) == 0x01000000
1060 && X_RD (prev_insn) == X_RS1 (insn))
1063 info->target = (unsigned) X_IMM22 (prev_insn) << 10;
|
| aarch64-opc.c | 5585 const struct aarch64_inst *prev_insn;
5590 prev_insn = insn_sequence->instr + (insn_sequence->num_added_insns - 1);
5592 prev_insn = NULL;
5594 if (prev_insn
5595 && (prev_insn->opcode->constraints & C_SCAN_MOPS_PME)
5596 && prev_insn->opcode != opcode - 1)
5601 mismatch_detail->data[0].s = prev_insn->opcode[1].name;
5602 mismatch_detail->data[1].s = prev_insn->opcode->name;
5609 if (is_new_section || !prev_insn || prev_insn->opcode != opcode - 1
5581 const struct aarch64_inst *prev_insn; local
[all...] |
| /src/external/gpl3/gcc/dist/gcc/ |
| loop-doloop.cc | 118 rtx_insn *prev_insn = prev_nondebug_insn (doloop_pat); local
128 if (prev_insn == NULL_RTX || !INSN_P (prev_insn))
132 if (GET_CODE (PATTERN (prev_insn)) == PARALLEL)
136 cmp_orig = XVECEXP (PATTERN (prev_insn), 0, 0);
152 inc = XVECEXP (PATTERN (prev_insn), 0, 1);
155 inc = PATTERN (prev_insn);
|
| dce.cc | 400 rtx_insn *insn, *prev_insn; local
462 for (insn = PREV_INSN (call_insn); insn; insn = prev_insn)
465 prev_insn = NULL;
467 prev_insn = PREV_INSN (insn);
|
| cfgrtl.cc | 273 rtx_insn *prev = PREV_INSN (current);
315 after = PREV_INSN (head);
744 insn = PREV_INSN (insn);
824 end = PREV_INSN (BB_HEAD (a));
826 insn = PREV_INSN (insn);
881 b_end = PREV_INSN (b_debug_start = b_end);
913 for (prev = PREV_INSN (a_end); ; prev = PREV_INSN (prev))
921 a_end = PREV_INSN (del_first);
957 reorder_insns_nobb (NEXT_INSN (a_end), PREV_INSN (b_debug_start)
5183 rtx_insn *prev_insn; local
[all...] |
| /src/external/gpl3/gcc.old/dist/gcc/ |
| loop-doloop.cc | 118 rtx_insn *prev_insn = prev_nondebug_insn (doloop_pat); local
128 if (prev_insn == NULL_RTX || !INSN_P (prev_insn))
132 if (GET_CODE (PATTERN (prev_insn)) == PARALLEL)
136 cmp_orig = XVECEXP (PATTERN (prev_insn), 0, 0);
152 inc = XVECEXP (PATTERN (prev_insn), 0, 1);
155 inc = PATTERN (prev_insn);
|
| dce.cc | 400 rtx_insn *insn, *prev_insn; local
462 for (insn = PREV_INSN (call_insn); insn; insn = prev_insn)
465 prev_insn = NULL;
467 prev_insn = PREV_INSN (insn);
|
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| sparc-dis.c | 1020 unsigned long prev_insn; local
1030 prev_insn = getword (buffer);
1042 if (is_delayed_branch (prev_insn))
1050 prev_insn = getword (buffer);
1059 if ((prev_insn & 0xc1c00000) == 0x01000000
1060 && X_RD (prev_insn) == X_RS1 (insn))
1063 info->target = (unsigned) X_IMM22 (prev_insn) << 10;
|
| /src/external/gpl3/gdb/dist/opcodes/ |
| sparc-dis.c | 992 unsigned long prev_insn; local
1002 prev_insn = getword (buffer);
1014 if (is_delayed_branch (prev_insn))
1022 prev_insn = getword (buffer);
1031 if ((prev_insn & 0xc1c00000) == 0x01000000
1032 && X_RD (prev_insn) == X_RS1 (insn))
1035 info->target = (unsigned) X_IMM22 (prev_insn) << 10;
|
| /src/external/gpl3/binutils/dist/gas/config/ |
| tc-d10v.c | 1115 static unsigned long prev_insn; variable
1628 write_1_short (prev_opcode, prev_insn, fixups->next);
1756 prev_insn = do_assemble (str, &prev_opcode);
1759 if (prev_insn == (unsigned long) -1)
1800 && (0 == write_2_short (prev_opcode, prev_insn, opcode, insn, extype,
1812 prev_insn = insn;
|
| tc-d30v.c | 1559 static long long prev_insn = -1; variable
1575 if ((prev_insn != -1) && prev_seg
1619 prev_insn = do_assemble (str, &prev_opcode, 1, 0);
1620 if (prev_insn == -1)
1656 if (prev_insn != -1
1660 && parallel_ok (&prev_opcode, (long) prev_insn,
1662 && write_2_short (&prev_opcode, (long) prev_insn,
1666 prev_insn = -1;
1676 if (prev_insn != -1 && (strcmp (prev_opcode.op->name, "nop") == 0))
1682 if (prev_insn != -1
[all...] |
| tc-frv.c | 679 struct vliw_insn_list *prev_insn = NULL;
699 prev_insn = curr_insn;
712 if (!prev_insn)
728 char *buffer = prev_insn->address;
742 prev_insn->next = NULL;
750 if (!prev_insn)
767 char *buffer = prev_insn->address;
781 prev_insn->next = NULL;
795 if (!prev_insn)
813 char *buffer = prev_insn->address
677 struct vliw_insn_list *prev_insn = NULL; local
[all...] |
| tc-m32r.c | 63 /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit
65 static m32r_insn prev_insn; variable
557 prev_insn.insn = NULL;
1275 if (prev_insn.insn || seen_relaxable_p)
1303 if (prev_insn.insn && seen_relaxable_p && optimize)
1322 prev_insn.insn is NULL when we're on a 32 bit boundary. */
1323 on_32bit_boundary_p = prev_insn.insn == NULL;
1346 && ! writes_to_pc (&prev_insn)
1347 && ! first_writes_to_seconds_operands (&prev_insn, &insn, false))
1349 if (can_make_parallel (&prev_insn, &insn) == NULL
[all...] |
| /src/external/gpl3/binutils.old/dist/gas/config/ |
| tc-d10v.c | 1115 static unsigned long prev_insn; variable
1628 write_1_short (prev_opcode, prev_insn, fixups->next);
1756 prev_insn = do_assemble (str, &prev_opcode);
1759 if (prev_insn == (unsigned long) -1)
1800 && (0 == write_2_short (prev_opcode, prev_insn, opcode, insn, extype,
1812 prev_insn = insn;
|
| tc-d30v.c | 1557 static long long prev_insn = -1; variable
1573 if ((prev_insn != -1) && prev_seg
1617 prev_insn = do_assemble (str, &prev_opcode, 1, 0);
1618 if (prev_insn == -1)
1654 if (prev_insn != -1
1658 && parallel_ok (&prev_opcode, (long) prev_insn,
1660 && write_2_short (&prev_opcode, (long) prev_insn,
1664 prev_insn = -1;
1674 if (prev_insn != -1 && (strcmp (prev_opcode.op->name, "nop") == 0))
1680 if (prev_insn != -1
[all...] |
| tc-frv.c | 679 struct vliw_insn_list *prev_insn = NULL;
699 prev_insn = curr_insn;
712 if (!prev_insn)
728 char *buffer = prev_insn->address;
742 prev_insn->next = NULL;
750 if (!prev_insn)
767 char *buffer = prev_insn->address;
781 prev_insn->next = NULL;
795 if (!prev_insn)
813 char *buffer = prev_insn->address
677 struct vliw_insn_list *prev_insn = NULL; local
[all...] |
| tc-m32r.c | 63 /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit
65 static m32r_insn prev_insn; variable
557 prev_insn.insn = NULL;
1275 if (prev_insn.insn || seen_relaxable_p)
1303 if (prev_insn.insn && seen_relaxable_p && optimize)
1322 prev_insn.insn is NULL when we're on a 32 bit boundary. */
1323 on_32bit_boundary_p = prev_insn.insn == NULL;
1346 && ! writes_to_pc (&prev_insn)
1347 && ! first_writes_to_seconds_operands (&prev_insn, &insn, false))
1349 if (can_make_parallel (&prev_insn, &insn) == NULL
[all...] |
| /src/external/gpl3/gcc/dist/gcc/config/sh/ |
| sh_treg_combine.cc | 827 rtx_insn *prev_insn = e.cstore.insn; local
839 if (reg_used_between_p (i->set_src (), prev_insn, i->insn))
847 prev_insn = i->insn;
1033 if (reg_set_between_p (m_ccreg, PREV_INSN (BB_HEAD (trace.bb ())),
1562 if (i == NULL || i == PREV_INSN (BB_HEAD (bb)))
1569 i = PREV_INSN (i);
1573 for (; i != NULL && i != PREV_INSN (BB_HEAD (bb)); i = PREV_INSN (i))
|
| /src/external/gpl3/gcc.old/dist/gcc/config/sh/ |
| sh_treg_combine.cc | 827 rtx_insn *prev_insn = e.cstore.insn; local
839 if (reg_used_between_p (i->set_src (), prev_insn, i->insn))
847 prev_insn = i->insn;
1033 if (reg_set_between_p (m_ccreg, PREV_INSN (BB_HEAD (trace.bb ())),
1562 if (i == NULL || i == PREV_INSN (BB_HEAD (bb)))
1569 i = PREV_INSN (i);
1573 for (; i != NULL && i != PREV_INSN (BB_HEAD (bb)); i = PREV_INSN (i))
|
| /src/external/gpl3/binutils/dist/bfd/ |
| coff-sh.c | 2347 unsigned int prev_insn = 0;
2363 prev_insn = bfd_get_16 (abfd, contents + i - 2);
2369 if (dsp && (prev_insn & 0xfc00) == 0xf800)
2372 /* Check if prev_insn is actually the field b of a parallel
2382 prev_op = sh_insn_info (prev_insn);
2385 prev_op = sh_insn_info (prev_insn);
2397 && ! sh_insns_conflict (prev_insn, prev_op, insn, op))
2402 there is a previous instruction; PREV_INSN is not
2403 itself a load/store instruction, and PREV_INSN and
2416 /* If the instruction before PREV_INSN has a dela
2345 unsigned int prev_insn = 0; local
[all...] |
| /src/external/gpl3/binutils.old/dist/bfd/ |
| coff-sh.c | 2349 unsigned int prev_insn = 0;
2365 prev_insn = bfd_get_16 (abfd, contents + i - 2);
2371 if (dsp && (prev_insn & 0xfc00) == 0xf800)
2374 /* Check if prev_insn is actually the field b of a parallel
2384 prev_op = sh_insn_info (prev_insn);
2387 prev_op = sh_insn_info (prev_insn);
2399 && ! sh_insns_conflict (prev_insn, prev_op, insn, op))
2404 there is a previous instruction; PREV_INSN is not
2405 itself a load/store instruction, and PREV_INSN and
2418 /* If the instruction before PREV_INSN has a dela
2347 unsigned int prev_insn = 0; local
[all...] |
| /src/external/gpl3/gdb.old/dist/bfd/ |
| coff-sh.c | 2349 unsigned int prev_insn = 0;
2365 prev_insn = bfd_get_16 (abfd, contents + i - 2);
2371 if (dsp && (prev_insn & 0xfc00) == 0xf800)
2374 /* Check if prev_insn is actually the field b of a parallel
2384 prev_op = sh_insn_info (prev_insn);
2387 prev_op = sh_insn_info (prev_insn);
2399 && ! sh_insns_conflict (prev_insn, prev_op, insn, op))
2404 there is a previous instruction; PREV_INSN is not
2405 itself a load/store instruction, and PREV_INSN and
2418 /* If the instruction before PREV_INSN has a dela
2347 unsigned int prev_insn = 0; local
[all...] |
| /src/external/gpl3/gdb/dist/bfd/ |
| coff-sh.c | 2349 unsigned int prev_insn = 0;
2365 prev_insn = bfd_get_16 (abfd, contents + i - 2);
2371 if (dsp && (prev_insn & 0xfc00) == 0xf800)
2374 /* Check if prev_insn is actually the field b of a parallel
2384 prev_op = sh_insn_info (prev_insn);
2387 prev_op = sh_insn_info (prev_insn);
2399 && ! sh_insns_conflict (prev_insn, prev_op, insn, op))
2404 there is a previous instruction; PREV_INSN is not
2405 itself a load/store instruction, and PREV_INSN and
2418 /* If the instruction before PREV_INSN has a dela
2347 unsigned int prev_insn = 0; local
[all...] |
