Searched refs:t0 (Results 1 - 25 of 197) sorted by relevance

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/src/sys/arch/hpcmips/hpcmips/
H A Dkloader_vr41.S40 lui t0, 0x1040 # Cu0 | BEV
41 mtc0 t0, $12
50 lw t0, 4(t7) # src
55 lw t3, 0(t0) # copy
58 addiu t0, t0, 4
70 li t0, 0x80000000
71 addu t1, t0, 1024 * 128
76 cache 0, 0(t0)
77 cache 0, 16(t0)
[all...]
H A Dkloader_tx39.S40 lui t0, 0x1040 # Cu0 | BEV
41 mtc0 t0, $12
50 lw t0, 4(t7) # src
55 lw t3, 0(t0) # copy
58 addiu t0, t0, 4
84 li t0, 0x80000000
85 addu t1, t0, t1
91 cache 0x0, 16(t0)
92 cache 0x0, 32(t0)
[all...]
H A Dlocore_machdep.S63 la t0, evr_hibernate
65 subu t0, t1 # t0 = length of this function
66 addu a0, t0
67 subu a1, t0
/src/sys/arch/sbmips/stand/common/
H A Dstart.S80 la t0,_edata /* t0 = address */
83 1: sw zero,0(t0)
84 sw zero,4(t0)
85 sw zero,8(t0)
86 sw zero,16(t0)
87 add t0,16
88 ble t0,t1,1b
98 li t0,0xBFC00000 /* transfer back to firmware */
99 j t0
[all...]
/src/sys/arch/evbmips/stand/sbmips/common/
H A Dstart.S80 la t0,_edata /* t0 = address */
83 1: sw zero,0(t0)
84 sw zero,4(t0)
85 sw zero,8(t0)
86 sw zero,16(t0)
87 add t0,16
88 ble t0,t1,1b
98 li t0,0xBFC00000 /* transfer back to firmware */
99 j t0
[all...]
/src/tests/lib/csu/arch/alpha/
H A Dh_initfini_align.S13 and sp, 7, t0
14 cmoveq t0, 1, v0
/src/lib/libc/time/
H A Ddifftime.c39 double t1 = time1, t0 = time0; local in function:difftime
40 return t1 - t0;
55 uintmax_t t1 = time1, t0 = time0; local in function:difftime
56 return time0 <= time1 ? t1 - t0 : dminus((double)(t0 - t1));
72 long double t1 = time1, t0 = time0; local in function:difftime
73 return t1 - t0;
/src/sys/arch/hpcmips/stand/lcboot/
H A Dstart.S124 li t0, 0xab000248 /* LEDCNTREG */
126 sh t1, (t0)
131 li t0, 0xab0000a2
133 sh t1, (t0)
144 li t0, 0xaa000000 /* BCUCNTREG1 */
146 sh t1, (t0)
154 li t0, 0xaa000010 /* BCURFCNTREG */
156 sh t1, (t0)
163 li t0, 0xaa00000c /* BCUSPEEDREG */
165 sh t1, (t0)
[all...]
/src/sys/external/isc/libsodium/dist/src/libsodium/crypto_generichash/blake2b/ref/
H A Dblake2b-load-avx2.h6 t0 = _mm256_unpacklo_epi64(m0, m1); \
8 b0 = _mm256_blend_epi32(t0, t1, 0xF0); \
13 t0 = _mm256_unpackhi_epi64(m0, m1); \
15 b0 = _mm256_blend_epi32(t0, t1, 0xF0); \
20 t0 = _mm256_unpacklo_epi64(m4, m5); \
22 b0 = _mm256_blend_epi32(t0, t1, 0xF0); \
27 t0 = _mm256_unpackhi_epi64(m4, m5); \
29 b0 = _mm256_blend_epi32(t0, t1, 0xF0); \
34 t0 = _mm256_unpacklo_epi64(m7, m2); \
36 b0 = _mm256_blend_epi32(t0, t
[all...]
/src/lib/libc/arch/riscv/sys/
H A Dgetcontext.S43 mv t0, a0
46 REG_S zero, UC_GREGS_RV(t0) /* success */
47 REG_S ra, UC_GREGS_PC(t0)
/src/common/lib/libc/arch/alpha/string/
H A Dbzero.S37 subq zero,a0,t0
38 and t0,7,t0 /* t0 = (0-size)%8 */
39 beq t0,bzero_nostart1
41 cmpult a1,t0,t1 /* if size > size%8 goto noshort */
49 lda t0,-1(zero) /* t0=-1 */
50 mskql t0,a1,t0 /* Ge
[all...]
H A Dbcopy.S84 xor SRCREG,DSTREG,t0
85 and t0,7,t0
87 bne t0,bcopy_different_alignment
102 subq SIZEREG,1,t0
104 bic t0,7,t0
105 beq t0,bcopy_samealign_lp_end
111 subq t0,8,t0
[all...]
/src/tests/kernel/arch/riscv/
H A Dcontextspfunc.S42 PTR_LA t0, _C_LABEL(contextsp) /* t0 := &contextsp */
43 PTR_S sp, 0(t0) /* contextsp := sp */
H A Dexecsp.S48 PTR_LA t0, _C_LABEL(startsp) /* t0 := &startsp */
49 PTR_S sp, 0(t0) /* startsp := sp */
60 PTR_LA t0, _C_LABEL(ctorsp) /* t0 := &ctorsp */
61 PTR_S sp, 0(t0) /* ctorsp := sp */
78 PTR_LA t0, _C_LABEL(mainsp) /* t0 := &mainsp */
79 PTR_S sp, 0(t0) /* mainsp := sp */
92 PTR_LA t0, _C_LABE
[all...]
H A Dsignalsphandler.S42 PTR_LA t0, _C_LABEL(signalsp) /* t0 := &signalsp */
43 PTR_S sp, 0(t0) /* signalsp := sp */
/src/sys/arch/cobalt/stand/boot/
H A Dstart.S66 li t0, 0x80000000
67 addu t1, t0, 32*1024 /* flush 32KB */
72 cache CACHE_R4K_I | CACHEOP_R4K_INDEX_INV, 0x000(t0)
73 cache CACHE_R4K_I | CACHEOP_R4K_INDEX_INV, 0x020(t0)
74 cache CACHE_R4K_I | CACHEOP_R4K_INDEX_INV, 0x040(t0)
75 cache CACHE_R4K_I | CACHEOP_R4K_INDEX_INV, 0x060(t0)
76 cache CACHE_R4K_I | CACHEOP_R4K_INDEX_INV, 0x080(t0)
77 cache CACHE_R4K_I | CACHEOP_R4K_INDEX_INV, 0x0a0(t0)
78 cache CACHE_R4K_I | CACHEOP_R4K_INDEX_INV, 0x0c0(t0)
79 cache CACHE_R4K_I | CACHEOP_R4K_INDEX_INV, 0x0e0(t0)
[all...]
/src/sys/arch/playstation2/playstation2/
H A Dlocore_machdep.S67 lw t0, 0(a1) /* I_MASK */
72 and t0, t0, t2
73 or t0, t0, t1 /* cur_mask */
75 xor ta0, ta0, t0
76 and t3, t3, t0
77 or t0, t3, ta0
78 and t3, t0, a0 /* INTC */
79 and ta0, t0, a
[all...]
/src/common/lib/libc/arch/mips/string/
H A Dstrcmp.S47 lbu t0, 0(a0) # get two bytes and compare them
49 beq t0, zero, LessOrEq # end of first string?
50 bne t0, t1, NotEq
51 lbu t0, 1(a0) # unroll loop
54 beq t0, zero, LessOrEq # end of first string?
56 beq t0, t1, 1b
58 subu v0, t0, t1
/src/common/lib/libc/arch/mips/atomic/
H A Datomic_and.S50 1: INT_LL t0, 0(a0)
52 and t0, a1
53 INT_SC t0, 0(a0)
54 beq t0, zero, 1b
66 move t0, v0
67 INT_SC t0, 0(a0)
68 beq t0, zero, 1b
78 1: REG_LL t0, 0(a0)
80 and t0, a1
81 REG_SC t0,
[all...]
H A Datomic_or.S47 1: INT_LL t0, 0(a0)
49 or t0, a1
50 INT_SC t0, 0(a0)
51 beq t0, zero, 1b
63 move t0, v0
64 INT_SC t0, 0(a0)
65 beq t0, zero, 1b
75 1: REG_LL t0, 0(a0)
77 or t0, a1
78 REG_SC t0,
[all...]
H A Datomic_dec.S49 li t0, -1
50 saa t0, (a0)
53 1: INT_LL t0, 0(a0)
55 INT_ADDU t0, -1
56 INT_SC t0, 0(a0)
57 beq t0, zero, 1b
70 move t0, v0
71 INT_SC t0, 0(a0)
72 beq t0, zero, 1b
82 li t0,
[all...]
H A Datomic_inc.S50 li t0, 1
51 saa t0, (a0)
54 1: INT_LL t0, 0(a0)
56 INT_ADDU t0, 1
57 INT_SC t0, 0(a0)
58 beq t0, zero, 1b
71 move t0, v0
72 INT_SC t0, 0(a0)
73 beq t0, zero, 1b
83 li t0,
[all...]
/src/common/lib/libc/arch/mips/gen/
H A Dbyte_swap_8.S67 li t0, 0xffff # t0 = 0x000000000000ffff
68 dsll t1, t0, 32 # t1 = 0x0000ffff00000000
69 or t0, t1 # t0 = 0x0000ffff0000ffff
70 dsll t2, t0, 8 # t2 = 0x00ffff0000ffff00
71 xor t2, t0 # t2 = 0x00ff00ff00ff00ff
79 and ta0, a1, t0 # ta0 = 0x000099880000ddcc
81 and ta1, t0 # ta1 = 0x0000bbaa0000ffee
98 srl t0, a
[all...]
/src/sys/arch/mips/rmi/
H A Drmixl_subr.S104 mfc0 t0, MIPS_COP_0_STATUS
105 REG_S t0, CALLFRAME_SIZ+2*SZREG(sp)
109 dsll32 t0, sp, 0 /* nuke upper half */
110 dsrl32 t0, t0, 0 /* " " " */
112 or sp, t0, t1 /* set MIPS_KSEG0_START */
118 REG_L t0, CALLFRAME_SIZ+2*SZREG(sp)
119 mtc0 t0, MIPS_COP_0_STATUS
139 li t0, MIPS_SR_KX
141 li t0,
[all...]
/src/sys/arch/evbmips/ingenic/
H A Dcpu_startup.S102 li t0, MIPS_KSEG0_START
103 ori t1, t0, CACHE_SIZE
106 1: cache CACHEOP_R4K_INDEX_STORE_TAG | CACHE_R4K_I, 0(t0)
107 cache CACHEOP_R4K_INDEX_STORE_TAG | CACHE_R4K_D, 0(t0)
108 addiu t0, t0, CACHE_LINESIZE
109 bne t0, t1, 1b
113 mfc0 t0, MIPS_COP_0_CONFIG, 0
114 ori t0, t0, MIPS3_TLB_ATTR_WB_NONCOHEREN
[all...]

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