| /src/sys/arch/evbarm/stand/boot2440/ |
| dm9000.c | 134 CSR_READ_1(struct local *l, int reg)
170 val = CSR_READ_1(l, PID0);
171 val |= CSR_READ_1(l, PID1) << 8;
172 val |= CSR_READ_1(l, VID0) << 16;
173 val |= CSR_READ_1(l, VID1) << 24;
195 val = CSR_READ_1(l, CHIPR);
197 val = CSR_READ_1(l, ISR);
214 } while (NCR_RST & CSR_READ_1(l, NCR));
223 } while (NCR_RST & CSR_READ_1(l, NCR));
226 (void) CSR_READ_1(l, NSR)
[all...] |
| /src/sys/arch/sandpoint/stand/altboot/ |
| nvt.c | 48 #define CSR_READ_1(l, r) in8((l)->csr+(r))
185 val = CSR_READ_1(l, VR_CTL1);
188 l->phy = CSR_READ_1(l, VR_MIICFG) & 0x1f;
191 en[0] = CSR_READ_1(l, VR_PAR0);
192 en[1] = CSR_READ_1(l, VR_PAR1);
193 en[2] = CSR_READ_1(l, VR_PAR2);
194 en[3] = CSR_READ_1(l, VR_PAR3);
195 en[4] = CSR_READ_1(l, VR_PAR4);
196 en[5] = CSR_READ_1(l, VR_PAR5);
322 v = CSR_READ_1(l, VR_MIISR)
[all...] |
| vge.c | 48 #define CSR_READ_1(l, r) in8((l)->csr+(r))
232 val = CSR_READ_1(l, VR_CTL1);
235 l->phy = CSR_READ_1(l, VR_MIICFG) & 0x1f;
238 en[0] = CSR_READ_1(l, VR_PAR0);
239 en[1] = CSR_READ_1(l, VR_PAR1);
240 en[2] = CSR_READ_1(l, VR_PAR2);
241 en[3] = CSR_READ_1(l, VR_PAR3);
242 en[4] = CSR_READ_1(l, VR_PAR4);
243 en[5] = CSR_READ_1(l, VR_PAR5);
282 while (--loop > 0 && (i = CSR_READ_1(l, VR_CAMCTL)) & CAMCTL_WR
[all...] |
| dsk.c | 59 #define CSR_READ_1(r) in8(r)
151 (void)CSR_READ_1(chan->alt);
152 (void)CSR_READ_1(chan->alt);
153 (void)CSR_READ_1(chan->alt);
154 (void)CSR_READ_1(chan->alt);
156 sts = CSR_READ_1(chan->cmd + _STS);
161 sts = CSR_READ_1(chan->cmd + _STS);
201 (void)CSR_READ_1(chan->alt);
205 (void)CSR_READ_1(chan->alt);
215 (void)CSR_READ_1(chan->alt)
[all...] |
| rge.c | 48 #define CSR_READ_1(l, r) in8((l)->csr+(r))
161 val = CSR_READ_1(l, RGE_CR);
179 en[0] = CSR_READ_1(l, RGE_IDR0);
180 en[1] = CSR_READ_1(l, RGE_IDR1);
181 en[2] = CSR_READ_1(l, RGE_IDR2);
182 en[3] = CSR_READ_1(l, RGE_IDR3);
183 en[4] = CSR_READ_1(l, RGE_IDR4);
184 en[5] = CSR_READ_1(l, RGE_IDR5);
195 val = CSR_READ_1(l, RGE_PHYSR);
|
| stg.c | 42 #define CSR_READ_1(l, r) in8((l)->csr+(r))
184 en[i] = CSR_READ_1(l, STGE_StationAddress0 + i);
255 reg = CSR_READ_1(l, STGE_PhyCtrl);
403 data |= !!(CSR_READ_1(l, STGE_PhyCtrl) & PC_MgmtData);
445 l->phyctrl_saved = CSR_READ_1(l, STGE_PhyCtrl) &
|
| fxp.c | 90 #define CSR_READ_1(l, r) in8((l)->iobase+(r))
377 ruscus = CSR_READ_1(l, FXP_CSR_SCB_RUSCUS);
504 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --loop > 0)
|
| skg.c | 47 #define CSR_READ_1(l, r) in8((l)->csr+(r))
239 en[i] = CSR_READ_1(l, SK_MAC0 + i);
|
| /src/sys/dev/ic/ |
| com.c | 137 #define CSR_READ_1(r, o) \
485 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) ||
486 (CSR_READ_1(regs, COM_REG_IIR) & 0x38))
681 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK)
683 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14)
702 lcr = CSR_READ_1(regsp, COM_REG_LCR);
705 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) {
708 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) {
740 lcr = CSR_READ_1(regsp, COM_REG_LCR);
745 iir1 = CSR_READ_1(regsp, COM_REG_IIR)
[all...] |
| wivar.h | 246 #define CSR_READ_1(sc, reg) \
268 #define CSR_READ_1(sc, reg) \
|
| rtl81x9.c | 147 CSR_READ_1(sc, RTK_EECMD) | (x))
151 CSR_READ_1(sc, RTK_EECMD) & ~(x))
210 if (CSR_READ_1(sc, RTK_EECMD) & RTK_EE_DATAOUT)
230 CSR_READ_1(sc, RTK_MII) | (x))
234 CSR_READ_1(sc, RTK_MII) & ~(x))
604 if ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET) == 0)
934 while ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_EMPTY_RXBUF) == 0) {
|
| rtl81x9var.h | 289 #define CSR_READ_1(sc, reg) \
|
| rtl8169.c | 243 *val = CSR_READ_1(sc, RTK_GMEDIASTAT);
341 *val = CSR_READ_1(sc, RTK_MEDIASTAT);
429 if ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET) == 0)
747 eaddr[i] = CSR_READ_1(sc, RTK_IDR0 + i);
774 eaddr[i] = CSR_READ_1(sc, RTK_IDR0 + i);
779 CSR_WRITE_1(sc, RTK_PMCH, CSR_READ_1(sc, RTK_PMCH) | 0x80);
2052 switch (CSR_READ_1(sc, RTK_CFG2_BUSFREQ) & 0x7) {
|
| i82557var.h | 352 #define CSR_READ_1(sc, reg) \
|
| i82557.c | 233 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
1086 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK);
1094 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
1535 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
2282 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) ==
|
| /src/sys/dev/pci/ |
| if_vge.c | 271 #define CSR_READ_1(sc, reg) \
275 CSR_WRITE_1((sc), (reg), CSR_READ_1((sc), (reg)) | (x))
282 CSR_WRITE_1((sc), (reg), CSR_READ_1((sc), (reg)) & ~(x))
387 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE)
415 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL)
437 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL)
455 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0)
473 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F))
488 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0)
511 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)
[all...] |
| if_ipwreg.h | 313 #define CSR_READ_1(sc, reg) \
|
| if_vr.c | 297 #define CSR_READ_1(sc, reg) \
330 CSR_READ_1(sc, reg) | (x))
334 CSR_READ_1(sc, reg) & ~(x))
375 return (CSR_READ_1(sc, VR_MIICMD));
471 rxfilt = CSR_READ_1(sc, VR_RXCFG);
1603 mac |= (eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i));
1610 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i);
|
| if_iwireg.h | 533 #define CSR_READ_1(sc, reg) \
|
| if_stge.c | 234 #define CSR_READ_1(_sc, reg) \
615 sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) &
2015 return (CSR_READ_1(sc, STGE_PhyCtrl));
|
| if_msk.c | 259 return CSR_READ_1(sc, reg);
1016 DPRINTFN(2, ("mskc_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR)));
|
| /src/sys/arch/evbarm/ixm1200/ |
| nappi_nppb.c | 58 #define CSR_READ_1(sc, reg) \
|
| /src/sys/dev/sdmmc/ |
| sbt.c | 39 #define CSR_READ_1(sc, reg) sdmmc_io_read_1((sc)->sc_sf, (reg))
331 status = CSR_READ_1(sc, SBT_REG_ISTAT);
|
| /src/sys/arch/arm/xscale/ |
| pxa2x0_mci.c | 145 #define CSR_READ_1(sc, reg) \
980 *cmd->c_buf++ = CSR_READ_1(sc, MMC_RXFIFO);
|
| /src/sys/arch/arm/imx/ |
| imxuart.c | 1741 msr = CSR_READ_1(regsp, IMXUART_REG_MSR);
2399 (void)CSR_READ_1(&sc->sc_regs, IMXUART_REG_IIR);
|
