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    Searched refs:MHz (Results 1 - 14 of 14) sorted by relevancy

  /src/sys/dev/ic/
decmonitors.c 38 #define MHz * 1000000
65 175 MHz },
70 75 MHz },
75 74 MHz },
80 69 MHz },
85 65 MHz },
90 50 MHz },
95 40 MHz },
110 135 MHz },
115 110 MHz },
    [all...]
  /src/sys/arch/arm/marvell/
kirkwood.c 238 #define MHz * 1000 * 1000
243 mvTclk = 200 MHz;
244 else /* 166MHz */
251 case 0x00000014: mvPclk = 600 MHz; break;
252 case 0x00000018: mvPclk = 800 MHz; break;
256 mvSysclk = 200 MHz;
259 case 0x00000002: mvPclk = 400 MHz; break;
260 case 0x00000008: mvPclk = 600 MHz; break;
261 case 0x00400008: mvPclk = 800 MHz; break;
262 case 0x0040000a: mvPclk = 1000 MHz; break
    [all...]
mv78xx0.c 215 #define MHz * 1000 * 1000
221 case 0x080: mvTclk = 200 MHz; break;
222 default: mvTclk = 200 MHz; break;
229 case 0x020: mvSysclk = 200 MHz; break;
232 case 0x080: mvSysclk = 400 MHz; break;
233 case 0x0a0: mvSysclk = 250 MHz; break;
234 case 0x0c0: mvSysclk = 300 MHz; break;
241 #undef MHz
dove.c 280 #define MHz * 1000 * 1000
286 case 0x00000000: mvTclk = 166 MHz; break;
287 case 0x00800000: mvTclk = 125 MHz; break;
293 case 0x000000a0: mvPclk = 1000 MHz; break;
294 case 0x000000c0: mvPclk = 933 MHz; break;
295 case 0x000000e0: mvPclk = 933 MHz; break;
296 case 0x00000100: mvPclk = 800 MHz; break;
297 case 0x00000120: mvPclk = 800 MHz; break;
298 case 0x00000140: mvPclk = 800 MHz; break;
299 case 0x00000160: mvPclk = 1067 MHz; break
    [all...]
  /src/sys/arch/ia64/ia64/
cpu.c 45 #define MHz 1000000L
46 #define GHz (1000L * MHz)
186 aprint_normal("%ld.%02ld-MHz ",
187 (processor_frequency + 4999) / MHz,
188 ((processor_frequency + 4999) / (MHz/100)) % 100);
  /src/sys/arch/mvme68k/stand/sboot/
oc_cksum.s 79 | Sun 3/50 (15MHz) 190 us/KB
80 | Sun 3/180 (16.6MHz) 175 us/KB
81 | Sun 3/60 (20MHz) 134 us/KB
82 | Sun 3/280 (25MHz) 95 us/KB
  /src/sys/arch/m68k/m68k/
oc_cksum.s 75 | Sun 3/50 (15MHz) 190 us/KB
76 | Sun 3/180 (16.6MHz) 175 us/KB
77 | Sun 3/60 (20MHz) 134 us/KB
78 | Sun 3/280 (25MHz) 95 us/KB
  /src/sys/arch/evbarm/stand/board/
s3c2800_vector.S 44 /* constans to get 200MHz FCLK */
58 #error define XTAL_CLK to 10, 8 or 6MHz
  /src/sys/arch/sandpoint/
README 32 On the PPMC, we assume a 100MHz clock.
41 - 33 MHz only
  /src/sys/external/bsd/drm2/dist/drm/i915/
i915_utils.h 443 #define MHz(x) KHz(1000 * (x))
  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_panel.c 1401 * CNP: PWM clock frequency is 19.2 MHz or 24 MHz.
1412 * BXT: PWM clock frequency = 19.2 MHz.
1422 * SCHICKEN_1 bit 0). PWM clock is 24 MHz.
1434 return DIV_ROUND_CLOSEST(MHz(24), pwm_freq_hz * mul);
1454 clock = MHz(135); /* LPT:H */
1456 clock = MHz(24); /* LPT:LP */
1513 * clocks ([DevCTG] 200MHz HRAW clocks) multiplied by 128 or 25MHz S0IX clocks
1514 * multiplied by 16. CHV uses a 19.2MHz S0IX clock
    [all...]
intel_dpll_mgr.c 1289 * Divide by MHz to match bsepc
1291 params->dco_integer = div_u64(dco_freq, 24 * MHz(1));
1294 params->dco_integer * MHz(1)) * 0x8000, MHz(1));
2297 u32 best_dco_centrality = U32_MAX; /* Spec meaning of 999999 MHz */
2510 /* Also used for 38.4 MHz values. */
2820 * The multiplication by 1000 is due to refclk MHz to KHz conversion. It
  /src/sys/arch/x86/x86/
est.c 100 /* Convert MHz and mV into IDs for passing to the MSR. */
101 #define ID16(MHz, mV, bus_clk) \
102 ((((MHz * 100 + 50) / bus_clk) << 8) | ((mV ? mV - 700 : 0) >> 4))
121 /* Ultra Low Voltage Intel Pentium M processor 900 MHz */
450 /* Intel Pentium M processor 710 1.4 GHz, 533 MHz FSB */
535 /* Intel Pentium M processor 730 1.6 GHz, 533 MHz FSB */
584 /* Intel Pentium M processor 740 1.73 GHz, 533 MHz FSB */
636 /* Intel Pentium M processor 750 1.86 GHz, 533 MHz FSB */
694 /* Intel Pentium M processor 760 2.0 GHz, 533 MHz FSB */
772 * VIA C7-M 500 MHz FSB, 400 MHz FSB, and ULV variants
    [all...]
  /src/sys/arch/amiga/amiga/
locore.s 1355 .long 12 | should be enough for 80 MHz 68060

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