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  /src/sys/rump/dev/lib/libpci_hdaudio/
Makefile 11 COMMENT=HDaudio PCI attachment
  /src/sys/arch/sandpoint/
README 24 S3/S4 - Mode 1: PMC w/o IDE (switches opposite, one nearest PCI
35 C ROM on PCI bus (DINK32 on mainboard)
44 -C--C PCI 33, Mem 66, PPC 266
45 -- 0.5 - 0.9 ns PCI hold time
46 C 25 ohm PCI drive strength
56 000A 0000 000F FFFF Compatibility Hole (programmable to go to PCI space
61 8000 0000 FCFF FFFF PCI memory space
62 FD00 0000 FDFF FFFF PCI/ISA memory space (see 5.8, CPU_FD_ALIAS_EN)
63 FE00 0000 FE7F FFFF PCI/ISA I/O space (Forwarded to PCI address spac
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  /src/sys/rump/dev/lib/libpci/
Makefile 8 .PATH: ${RUMPTOP}/../dev/pci
11 COMMENT=PCI bus support
13 IOCONF= PCI.ioconf
15 SRCS+= pci.c pci_map.c pci_quirks.c pci_subr.c pci_stub.c pci_usrreq.c
  /src/sys/rump/dev/lib/libpci_usbhc/
Makefile 6 .PATH: ${RUMPTOP}/../dev/pci ${RUMPTOP}/../dev/usb
9 COMMENT=PCI USB host controller drivers
  /src/sys/arch/arm/marvell/
orionreg.h 34 * Ver GbE SATA USB PCI PCIe IDMA XORE CESA
51 #define ORION_UNITID_PCI 0x3 /* PCI registers */
87 #define ORION_IRQ_PEX0ERR 10 /* PCI Express error */
93 #define ORION_IRQ_PCIERR 15 /* PCI error */
174 * PCI Express Interface Registers
175 * or PCI Interface Registers
178 #define ORION_PCI_BASE (ORION_UNITID2PHYS(PCI)) /* 0x30000 */
  /src/sys/arch/x86/conf/
files.x86 13 # PCI fixup options
160 file arch/x86/pci/pci_machdep.c pci
161 #file arch/x86/pci/pci_ranges.c pci
162 file arch/x86/pci/pci_intr_machdep.c pci
163 file arch/x86/pci/pci_msi_machdep.c pci & ! no_pci_msi_msix
164 file arch/x86/pci/msipic.c pci & ! no_pci_msi_msi
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  /src/sys/external/bsd/gnu-efi/dist/inc/
efi_pxe.h 940 // PCI and PC Card NICs are both identified using bus, device
947 // See S/W UNDI ROMID structure definition for PCI and
958 } PCI, PCC;
1136 // For PCI bus devices, this field is set to PXE_BUSTYPE_PCI.
1141 // This identifies the PCI network device that this UNDI interface
1149 // This is a copy of the PCI configuration space for this
1200 PXE_PCI_CONFIG_INFO pci; member in union:u_pxe_db_get_config_info
  /src/sys/arch/ia64/stand/common/
help.common 314 set hw.{acpi,pci}.host_start_mem=<value>
316 Sets the lowest address that the pci code will assign
318 to assign (like from a pci bridge). This is only useful
319 in older systems without a pci bridge. Also, it only
326 set hw.pci.enable_io_modes=<value>
328 Enable PCI resources which are left off by some BIOSes
  /src/sys/arch/x86/pci/
pci_machdep.c 64 * Machine-specific functions for PCI autoconfiguration.
66 * On PCs, there are two methods of generating PCI configuration cycles.
97 #include <dev/pci/pcivar.h>
98 #include <dev/pci/pcireg.h>
99 #include <dev/pci/pccbbreg.h>
100 #include <dev/pci/pcidevs.h>
101 #include <dev/pci/ppbvar.h>
102 #include <dev/pci/genfb_pcivar.h>
118 #include "pci.h"
153 #include <dev/pci/puccn.h
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  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/device/
nouveau_nvkm_engine_device_base.c 114 .pci = nv04_pci_new,
135 .pci = nv04_pci_new,
157 .pci = nv04_pci_new,
177 .pci = nv04_pci_new,
199 .pci = nv04_pci_new,
221 .pci = nv04_pci_new,
243 .pci = nv04_pci_new,
265 .pci = nv04_pci_new,
287 .pci = nv04_pci_new,
309 .pci = nv04_pci_new
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  /src/sys/dev/ic/
bwi.c 105 #include <dev/pci/pcireg.h>
106 #include <dev/pci/pcidevs.h>
569 CLKSRC(PCI)
1684 * then the card's PCI revision must >= 0x51
6531 /* [TRC: XXX This looks totally wrong -- what's PCI doing in here?] */
6947 * 1) Bus (PCI/PCIE) regwin
7003 * Tell bus to generate requested interrupts (PCI and Cardbus only).
7172 src == BWI_CLKSRC_PCI ? "PCI" :
10119 return ("PCI");

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