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Searched refs:RB_NO_UPDATE (Results 1 - 18 of 18) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vcn_v2_5.c	`860 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1040 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1254 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);`
amdgpu_uvd_v5_0.c	`403 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);`
amdgpu_vcn_v1_0.c	`911 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1069 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);`
amdgpu_vcn_v2_0.c	`847 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1008 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);`
amdgpu_uvd_v6_0.c	`821 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);`
amdgpu_uvd_v7_0.c	`1073 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);`
sid.h	`1281 #define RB_NO_UPDATE (1 << 27)`
/src/sys/external/bsd/drm2/dist/drm/radeon/
rv770d.h	`354 #define RB_NO_UPDATE (1 << 27)`
nid.h	`489 #define RB_NO_UPDATE (1 << 27)`
cikd.h	`1308 #define RB_NO_UPDATE (1 << 27)`
sid.h	`1252 #define RB_NO_UPDATE (1 << 27)`
evergreend.h	`481 #define RB_NO_UPDATE (1 << 27)`
r600d.h	`200 #define RB_NO_UPDATE (1 << 27)`
radeon_rv770.c	`1110 RB_NO_UPDATE \| RB_BLKSZ(15) \| RB_BUFSZ(3));`
radeon_r600.c	`2690 RB_NO_UPDATE \| RB_BLKSZ(15) \| RB_BUFSZ(3)); 2788 tmp \|= RB_NO_UPDATE;`
radeon_evergreen.c	`2983 RB_NO_UPDATE \| RB_BLKSZ(15) \| RB_BUFSZ(3)); 3115 tmp \|= RB_NO_UPDATE;`
radeon_si.c	`3695 tmp \|= RB_NO_UPDATE;`
radeon_cik.c	`4116 tmp \|= RB_NO_UPDATE;`

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