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    Searched refs:SMC_SYSCON_RESET_CNTL (Results 1 - 12 of 12) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_si_smc.c 118 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
122 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
134 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL) |
136 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
160 u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
sid.h 72 #define SMC_SYSCON_RESET_CNTL 0x80000000
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_si_smc.c 120 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
124 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
136 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
138 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
168 u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
radeon_ci_smc.c 121 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
124 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
129 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
132 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
cikd.h 74 #define SMC_SYSCON_RESET_CNTL 0x80000000
sid.h 70 #define SMC_SYSCON_RESET_CNTL 0x80000000
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_vegam_smumgr.c 114 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
128 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
149 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
152 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
173 SMC_SYSCON_RESET_CNTL,
187 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
amdgpu_fiji_smumgr.c 113 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
128 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
181 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
196 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
amdgpu_polaris10_smumgr.c 213 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
227 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
248 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
251 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
272 SMC_SYSCON_RESET_CNTL,
286 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
amdgpu_tonga_smumgr.c 108 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
124 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
174 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
190 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
amdgpu_iceland_smumgr.c 117 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
125 SMC_SYSCON_RESET_CNTL,
amdgpu_ci_smumgr.c 1906 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 0);
2366 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 1);

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