| /src/sys/external/bsd/compiler_rt/dist/test/builtins/Unit/arm/ |
| aeabi_cdcmple_test.c | 50 union cpsr cpsr = { .value = cpsr_value }; local in function:test__aeabi_cdcmple
51 if (expected_z != cpsr.flags.z || expected_c != cpsr.flags.c) {
53 a, b, cpsr.flags.z, cpsr.flags.c, expected_z, expected_c);
57 cpsr.value = r_cpsr_value;
58 if (expected_z != cpsr.flags.z || expected_c != cpsr.flags.c) {
60 a, b, cpsr.flags.z, cpsr.flags.c, expected_z, expected_c)
[all...] |
| aeabi_cfcmple_test.c | 50 union cpsr cpsr = { .value = cpsr_value }; local in function:test__aeabi_cfcmple
51 if (expected_z != cpsr.flags.z || expected_c != cpsr.flags.c) {
53 a, b, cpsr.flags.z, cpsr.flags.c, expected_z, expected_c);
57 cpsr.value = r_cpsr_value;
58 if (expected_z != cpsr.flags.z || expected_c != cpsr.flags.c) {
60 a, b, cpsr.flags.z, cpsr.flags.c, expected_z, expected_c)
[all...] |
| aeabi_cdcmpeq_test.c | 27 union cpsr cpsr = { .value = cpsr_value }; local in function:test__aeabi_cdcmpeq
28 if (expected != cpsr.flags.z) {
30 a, b, cpsr.flags.z, expected);
|
| aeabi_cfcmpeq_test.c | 27 union cpsr cpsr = { .value = cpsr_value }; local in function:test__aeabi_cfcmpeq
28 if (expected != cpsr.flags.z) {
30 a, b, cpsr.flags.z, expected);
|
| call_apsr.h | 22 union cpsr { union
|
| /src/sys/arch/arm/arm32/ |
| setcpsr.S | 41 * Miscellaneous routines to play with the CPSR register
52 /* Sets and clears bits in the CPSR register
59 mrs r3, cpsr /* Set the CPSR */
64 mov r0, r3 /* Return the old CPSR */
70 /* Gets the CPSR register
72 * Returns the CPSR in r0
76 mrs r0, cpsr /* Get the CPSR */
|
| setstack.S | 63 mrs r3, cpsr /* Switch to the appropriate mode */
83 mrs r3, cpsr /* Switch to the appropriate mode */
|
| spl.S | 64 mrs r4, cpsr
84 mrs r4, cpsr
107 mrs r4, cpsr
|
| /src/sys/arch/arm/xscale/ |
| pxa2x0_apm_asm.S | 165 mrs r2, spsr /* Load SVC saved CPSR. */
166 str r2, [r3], #4 /* Save SVC saved CPSR. */
170 msr cpsr, r1 /* Enter FIQ mode. */
171 mrs r2, spsr /* Load FIQ mode saved CPSR. */
175 msr cpsr, r1 /* Enter IRQ mode. */
176 mrs r0, spsr /* Load IRQ mode saved CPSR. */
180 msr cpsr, r1 /* Enter ABT mode. */
181 mrs r0, spsr /* Load ABT mode saved CPSR. */
185 msr cpsr, r1 /* Enter UND mode. */
186 mrs r0, spsr /* Load UND mode saved CPSR. *
[all...] |
| /src/sys/arch/arm/arm/ |
| cpufunc_asm_arm11x6.S | 82 mrs Rtmp2, cpsr; \
149 mrs r2, cpsr /* save the CPSR */
181 mrs r2, cpsr /* save the CPSR */
|
| cpufunc_asm_sa11x0.S | 79 * We must disable interrupts in the CPSR so that we can
83 mrs r3, cpsr /* 6 */
|
| fiq_subr.S | 49 mrs r2, cpsr ; \
|
| cpufunc_asm_sheeva.S | 43 mrs r4, cpsr
85 mrs r4, cpsr
127 mrs r4, cpsr
169 mrs r4, cpsr
218 mrs r4, cpsr
264 mrs r4, cpsr
308 mrs r4, cpsr
|
| /src/sys/arch/arm/include/ |
| locore.h | 76 mrs rTMP, cpsr ; \
81 mrs rTMP, cpsr ; \
86 mrs rTMP, cpsr ; \
91 mrs rTMP, cpsr ; \
|
| /src/sys/arch/arm/include/arm32/ |
| frame.h | 143 mrs rb, cpsr /* fetch CPSR */
210 GET_CPSR(r6) /* save CPSR */ ;\
237 GET_CPSR(r6) /* save CPSR */ ;\
343 mrs r0, cpsr; /* Get the CPSR */ \
344 str r0, [sp, #(-TF_R4)]! /* Push the CPSR on the stack */
357 mrs rX, cpsr; /* Get the CPSR */ \
373 mrs r0, cpsr; /* Get the CPSR */
[all...] |
| /src/sys/arch/evbarm/smdk2xx0/ |
| smdk2410_start.S | 60 mrs r0, cpsr
62 msr cpsr, r0
|
| /src/sys/arch/evbarm/stand/board/ |
| s3c2410_vector.S | 65 mrs r0, cpsr
69 msr cpsr, r0
|
| s3c2800_vector.S | 97 mrs r0, cpsr
101 msr cpsr, r0
|
| /src/sys/arch/evbarm/stand/boot2440/ |
| entry.S | 58 mrs r0, cpsr
60 msr cpsr, r0
|
| /src/sys/arch/zaurus/stand/zbsdmod/ |
| zbsdmod.c | 83 static int cpsr; variable in typeref:typename:int
155 __asm volatile ("mrs %0, cpsr" : "=r" (cpsr));
156 cpsr |= 0xc0; /* set FI */
157 __asm volatile ("msr cpsr_all, %0" :: "r" (cpsr));
|
| /src/sys/arch/arm/iomd/ |
| iomd_irqhandler.c | 380 u_int cpsr;
382 cpsr = SetCPSR(mask, mask);
383 return cpsr;
|
| /src/sys/arch/arm/ofw/ |
| ofw_irq.S | 123 * spsr_svc // cpsr of interrupted context
252 mrs r0, cpsr /* Enable IRQ's */
320 mrs r0, cpsr
377 /*assert((cpsr & PSR_MODE) == PSR_IRQ32_MODE);*/
396 * spsr // cpsr of interrupted context
448 mrs r3, cpsr
|
| /src/sys/arch/arm/sa11x0/ |
| sa11x0_irq.S | 154 mrs r0, cpsr /* Enable IRQs */
234 mrs r0, cpsr
263 mrs r1, cpsr
276 /* Restore old cpsr and exit */
|
| /src/sys/arch/shark/isa/ |
| isa_irq.S | 209 mrs r0, cpsr /* Enable IRQ's */
273 mrs r0, cpsr
303 mrs r3, cpsr
372 /* Restore old cpsr and exit */
|
| /src/sys/arch/hpcarm/hpcarm/ |
| locore.S | 58 mrs r4, cpsr
196 mrs r2, cpsr
248 * part of doing a system dump, we need to save registers and cpsr onto the
256 mrs r0, cpsr
|
