| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_cursor.c | 44 cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset);
49 WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
51 cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset);
56 WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
58 cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset);
63 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock);
73 WREG32_IDX(EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset,
77 WREG32_IDX(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset,
104 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
106 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
[all...] |
| radeon_display.c | 62 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
64 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
65 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
66 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
68 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
69 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
70 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
88 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1);
100 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
102 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0)
[all...] |
| radeon_atombios_crtc.c | 1400 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0);
1402 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1404 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1406 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1408 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1410 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1411 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1418 WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset,
1425 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1426 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0)
[all...] |
| radeon_legacy_crtc.c | 49 WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0);
50 WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0);
51 WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0);
389 uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0; local in function:radeon_crtc_do_set_base
560 crtc_offset = (u32)base;
562 WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);
570 WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);
571 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);
572 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch)
[all...] |
| radeon_rs600.c | 126 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
131 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
134 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset,
136 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
138 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
143 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
151 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
159 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) &
332 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
334 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp)
[all...] |
| radeon_rv515.c | 719 int index_reg = 0x6578 + crtc->crtc_offset;
720 int data_reg = 0x657c + crtc->crtc_offset;
722 WREG32(0x659C + crtc->crtc_offset, 0x0);
723 WREG32(0x6594 + crtc->crtc_offset, 0x705);
724 WREG32(0x65A4 + crtc->crtc_offset, 0x10001);
725 WREG32(0x65D8 + crtc->crtc_offset, 0x0);
726 WREG32(0x65B0 + crtc->crtc_offset, 0x0);
727 WREG32(0x65C0 + crtc->crtc_offset, 0x0);
728 WREG32(0x65D4 + crtc->crtc_offset, 0x0);
|
| radeon_rv770.c | 816 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
821 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
824 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset,
833 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
835 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
840 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
848 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
856 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) &
|
| radeon_atombios_encoders.c | 2091 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,
2094 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2097 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
2100 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2103 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
2106 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
|
| radeon_evergreen.c | 1353 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
1429 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset,
1431 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1433 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1436 RREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset);
1452 return !!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) &
1687 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
1689 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
1712 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
1714 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp)
[all...] |
| radeon_si.c | 2011 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset,
2442 arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
2446 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
2447 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
2451 tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
2454 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
2455 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
2459 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3);
2462 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
2463 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt)
[all...] |
| radeon_mode.h | 335 uint32_t crtc_offset; member in struct:radeon_crtc
|
| radeon_r100.c | 175 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
179 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
187 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
205 return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) &
|
| radeon_cik.c | 8867 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
8917 WREG32(LB_MEMORY_CTRL + radeon_crtc->crtc_offset,
9415 wm_mask = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);
9419 WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);
9420 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
9424 tmp = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);
9427 WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);
9428 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
9432 WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, wm_mask);
|
| radeon_r600.c | 353 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_dce_v10_0.c | 248 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
251 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
253 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
256 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
259 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
262 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
582 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
633 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
635 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
1130 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
[all...] |
| amdgpu_dce_v11_0.c | 266 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
269 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
271 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
274 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
277 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
280 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
608 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
659 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
661 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
1156 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
[all...] |
| amdgpu_dce_v6_0.c | 202 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
205 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
208 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
210 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
214 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
459 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
962 arb_control3 = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);
966 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp);
967 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
971 tmp = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);
[all...] |
| amdgpu_dce_v8_0.c | 195 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
198 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
201 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
204 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
207 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
519 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
570 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset,
1065 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1069 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1070 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
[all...] |
| amdgpu_mode.h | 387 uint32_t crtc_offset; member in struct:amdgpu_crtc
|
| /src/sys/external/bsd/drm/dist/shared-core/ |
| r128_drv.h | 97 u32 crtc_offset; member in struct:drm_r128_private
|
| r128_state.c | 1273 dev_priv->crtc_offset = R128_READ(R128_CRTC_OFFSET);
1292 R128_WRITE(R128_CRTC_OFFSET, dev_priv->crtc_offset);
|
| /src/sys/external/bsd/drm2/dist/drm/r128/ |
| r128_drv.h | 109 u32 crtc_offset; member in struct:drm_r128_private
|
| r128_state.c | 1241 dev_priv->crtc_offset = R128_READ(R128_CRTC_OFFSET);
1260 R128_WRITE(R128_CRTC_OFFSET, dev_priv->crtc_offset);
|
