| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/nxp/imx/ |
| imx53-usbarmory.dts | 153 lltc,fb-voltage-divider = <100000 158000>;
162 lltc,fb-voltage-divider = <180000 191000>;
171 lltc,fb-voltage-divider = <270000 100000>;
180 lltc,fb-voltage-divider = <511000 158000>;
188 lltc,fb-voltage-divider = <100000 158000>;
196 lltc,fb-voltage-divider = <180000 191000>;
|
| imx6qdl-gw551x.dtsi | 358 lltc,fb-voltage-divider = <127000 200000>;
369 lltc,fb-voltage-divider = <221000 200000>;
380 lltc,fb-voltage-divider = <127000 200000>;
391 lltc,fb-voltage-divider = <200000 56200>;
402 lltc,fb-voltage-divider = <301000 200000>;
420 lltc,fb-voltage-divider = <634000 200000>;
|
| imx6qdl-gw553x.dtsi | 346 lltc,fb-voltage-divider = <127000 200000>;
357 lltc,fb-voltage-divider = <221000 200000>;
368 lltc,fb-voltage-divider = <127000 200000>;
379 lltc,fb-voltage-divider = <200000 56200>;
390 lltc,fb-voltage-divider = <301000 200000>;
408 lltc,fb-voltage-divider = <634000 200000>;
|
| imx6qdl-gw5903.dtsi | 378 lltc,fb-voltage-divider = <301000 200000>;
389 lltc,fb-voltage-divider = <221000 200000>;
400 lltc,fb-voltage-divider = <127000 200000>;
412 lltc,fb-voltage-divider = <127000 200000>;
424 lltc,fb-voltage-divider = <100000 261000>;
434 lltc,fb-voltage-divider = <634000 200000>;
|
| imx6qdl-gw5904.dtsi | 452 lltc,fb-voltage-divider = <127000 200000>;
463 lltc,fb-voltage-divider = <301000 200000>;
474 lltc,fb-voltage-divider = <127000 200000>;
485 lltc,fb-voltage-divider = <221000 200000>;
496 lltc,fb-voltage-divider = <487000 200000>;
506 lltc,fb-voltage-divider = <634000 200000>;
|
| imx6qdl-gw560x.dtsi | 491 lltc,fb-voltage-divider = <221000 200000>;
502 lltc,fb-voltage-divider = <243000 261000>;
514 lltc,fb-voltage-divider = <301000 200000>;
525 lltc,fb-voltage-divider = <78700 200000>;
543 lltc,fb-voltage-divider = <634000 200000>;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn20/ |
| dcn20_clk_mgr.h | 48 uint32_t dentist_get_did_from_divider(int divider);
|
| amdgpu_dcn20_clk_mgr.c | 77 uint32_t dentist_get_did_from_divider(int divider)
82 if (divider < DENTIST_DIVIDER_RANGE_2_START) {
83 if (divider < DENTIST_DIVIDER_RANGE_1_START)
87 + (divider - DENTIST_DIVIDER_RANGE_1_START)
89 } else if (divider < DENTIST_DIVIDER_RANGE_3_START) {
91 + (divider - DENTIST_DIVIDER_RANGE_2_START)
93 } else if (divider < DENTIST_DIVIDER_RANGE_4_START) {
95 + (divider - DENTIST_DIVIDER_RANGE_3_START)
99 + (divider - DENTIST_DIVIDER_RANGE_4_START)
463 /* Convert DPREFCLK DFS Slice DID to actual divider*/
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_cdclk.c | 463 * CCK divider into the Punit register.
575 u32 divider; local
577 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1,
580 /* adjust cdclk divider */
583 val |= divider;
587 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
1171 { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 },
1172 { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 },
1173 { .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 },
1174 { .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 }
1359 u32 divider; local
1501 u32 val, divider; local
2543 int divider, fraction; local
[all...] |
| intel_cdclk.h | 23 u8 divider; /* CD2X divider * 2 */ member in struct:intel_cdclk_vals
|
| intel_lvds.c | 64 int divider; member in struct:intel_lvds_pps
176 pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val);
201 "divider %d port %d powerdown_on_reset %d\n",
203 pps->divider, pps->port, pps->powerdown_on_reset);
227 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) |
|
| /src/sys/dev/marvell/ |
| mvspi.c | 157 uint32_t divider; local
196 divider = spr * (1 << sppr);
198 if ((mvTclk / divider) > speed)
202 if ((mvTclk / divider) == speed) {
210 if ((speed - (mvTclk / divider)) < min_baud_offset) {
211 min_baud_offset = (speed - (mvTclk / divider));
|
| /src/sys/dev/i2c/ |
| sensirion_voc_algorithm.c | 136 uint32_t divider = (uint32_t)((b >= 0) ? b : (-b)); local
142 while (divider < remainder) {
143 divider <<= 1;
152 if (divider & 0x80000000) {
154 // We know that divider's bottom bit is 0 here.
155 if (remainder >= divider) {
157 remainder -= divider;
159 divider >>= 1;
165 if (remainder >= divider) {
167 remainder -= divider;
[all...] |
| /src/sys/arch/arm/rockchip/ |
| rk_spi.c | 262 uint16_t divider; local
264 divider = (sc->sc_spi_freq / speed) & ~1;
265 if (divider < 2) {
269 divider = 2;
297 SPIREG_WRITE(sc, SPI_BAUDR, divider);
|
| /src/usr.bin/units/ |
| units.c | 347 char *divider, *slash; local
397 divider = strchr(item, '|');
398 if (divider) {
399 *divider = 0;
405 if (endptr != divider) {
414 num = strtod(divider + 1, &endptr);
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| r600_dpm.h | 183 u32 index, u32 divider);
185 u32 index, u32 divider);
187 u32 index, u32 divider);
|
| radeon_trinity_dpm.c | 618 u32 index, u32 divider)
625 value |= DS_DIV(divider);
630 u32 index, u32 divider)
637 value |= DS_SH_DIV(divider);
1835 u32 divider; local
1838 divider = did * 25;
1840 divider = (did - 64) * 50 + 1600;
1842 divider = (did - 96) * 100 + 3200;
1844 divider = 128 * 100;
1848 return ((pi->sys_info.dentist_vco_freq * 100) + (divider - 1)) / divider
[all...] |
| radeon_legacy_crtc.c | 770 int divider; member in struct:__anon5538
838 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
839 if (post_div->divider == post_divider)
843 if (!post_div->divider)
945 This appears to related to the PLL divider registers (fail to lock?).
991 /* R300 uses ref_div_acc field as real ref divider */
|
| radeon_sumo_dpm.c | 479 u32 index, u32 divider)
486 SCLK_FSTATE_0_DIV(divider), ~SCLK_FSTATE_0_DIV_MASK);
489 SCLK_FSTATE_1_DIV(divider), ~SCLK_FSTATE_1_DIV_MASK);
492 SCLK_FSTATE_2_DIV(divider), ~SCLK_FSTATE_2_DIV_MASK);
495 SCLK_FSTATE_3_DIV(divider), ~SCLK_FSTATE_3_DIV_MASK);
499 u32 index, u32 divider)
507 dpm_ctrl |= (divider << (index * 3));
513 u32 index, u32 divider)
521 dpm_ctrl |= (divider << (index * 3));
|
| radeon_r600_dpm.c | 484 u32 index, u32 divider)
487 STEP_0_SPLL_POST_DIV(divider), ~STEP_0_SPLL_POST_DIV_MASK);
491 u32 index, u32 divider)
494 STEP_0_SPLL_REF_DIV(divider), ~STEP_0_SPLL_REF_DIV_MASK);
498 u32 index, u32 divider)
501 STEP_0_SPLL_FB_DIV(divider), ~STEP_0_SPLL_FB_DIV_MASK);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/ |
| opp.h | 241 uint32_t divider; /* (actually HW range is min/divider; divider !=0) */ member in struct:hw_adjustment_range
|
| /src/usr.bin/diff3/ |
| diff3.c | 143 static const char *divider = "======="; variable
604 printf("%s\n", divider);
663 printf("%s\n.\n", divider);
684 printf("%s\n", divider);
735 printf("%s\n", divider);
755 printf("%s\n", divider);
|
| /src/sys/arch/arm/nxp/ |
| imx6_ccm.c | 425 u_int divider = uimax(1, rate_parent / rate); local
440 if (div->tbl[i] == divider)
448 v |= __SHIFTIN(divider - 1, div->mask);
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/clk/ |
| nouveau_nvkm_subdev_clk_gk20a.c | 97 u32 divider; local
100 divider = pll->m * clk->pl_to_div(pll->pl);
102 return rate / divider / 2;
310 /* split VCO-to-bypass jump in half by setting out divider 1:2 */
313 /* Intentional 2nd write to assure linear divider operation */
327 /* restore out divider 1:1 */
331 /* Intentional 2nd write to assure linear divider operation */
|
| /src/sys/arch/arm/broadcom/ |
| bcm2835_bsc.c | 103 u_int divider = howmany(sc->sc_frequency, sc->sc_clkrate); local
105 __SHIFTIN(divider, BSC_DIV_CDIV));
|
