| /src/sys/external/bsd/drm2/dist/drm/amd/amdkfd/ |
| kfd_packet_manager_v9.c | 59 packet->sq_shader_tba_lo = lower_32_bits(qpd->tba_addr >> 8);
66 packet->sq_shader_tma_lo = lower_32_bits(qpd->tma_addr >> 8);
70 packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area);
74 lower_32_bits(vm_page_table_base_addr);
113 packet->ordinal2 = lower_32_bits(ib);
138 packet->gws_mask_lo = lower_32_bits(res->gws_mask);
141 packet->queue_mask_lo = lower_32_bits(res->queue_mask);
200 lower_32_bits(q->gart_mqd_addr);
206 lower_32_bits((uint64_t)q->properties.write_ptr);
309 packet->addr_lo = lower_32_bits((uint64_t)fence_address)
[all...] |
| kfd_packet_manager_vi.c | 73 packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area);
112 packet->ordinal2 = lower_32_bits(ib);
137 packet->gws_mask_lo = lower_32_bits(res->gws_mask);
140 packet->queue_mask_lo = lower_32_bits(res->queue_mask);
190 lower_32_bits(q->gart_mqd_addr);
196 lower_32_bits((uint64_t)q->properties.write_ptr);
288 packet->addr_lo = lower_32_bits((uint64_t)fence_address);
290 packet->data_lo = lower_32_bits((uint64_t)fence_value);
|
| kfd_mqd_manager_vi.c | 120 m->cp_mqd_base_addr_lo = lower_32_bits(addr);
134 m->compute_tba_lo = lower_32_bits(q->tba_addr >> 8);
136 m->compute_tma_lo = lower_32_bits(q->tma_addr >> 8);
146 lower_32_bits(q->ctx_save_restore_area_address);
188 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
191 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
193 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr);
219 lower_32_bits(q->eop_ring_buffer_address >> 8);
361 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8);
363 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr)
[all...] |
| kfd_mqd_manager_v10.c | 116 m->cp_mqd_base_addr_lo = lower_32_bits(addr);
132 lower_32_bits(q->ctx_save_restore_area_address);
181 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
184 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
186 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr);
207 lower_32_bits(q->eop_ring_buffer_address >> 8);
338 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8);
340 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
|
| kfd_mqd_manager_v9.c | 151 m->cp_mqd_base_addr_lo = lower_32_bits(addr);
172 lower_32_bits(q->ctx_save_restore_area_address);
218 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
221 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
223 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr);
246 lower_32_bits(q->eop_ring_buffer_address >> 8);
381 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8);
383 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
|
| kfd_mqd_manager_cik.c | 120 m->cp_mqd_base_addr_lo = lower_32_bits(addr);
211 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
213 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
252 m->sdma_rlc_rb_base = lower_32_bits(q->queue_address >> 8);
254 m->sdma_rlc_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
334 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
336 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
|
| /src/sys/external/bsd/drm2/dist/drm/i915/gt/ |
| intel_lrc_reg.h | 41 (reg_state__)[CTX_PDP ## n ## _LDW] = lower_32_bits(addr__); \
48 (reg_state__)[CTX_PDP0_LDW] = lower_32_bits(addr__); \
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/ |
| nouveau_nvc0_fence.c | 43 OUT_RING (chan, lower_32_bits(virtual));
59 OUT_RING (chan, lower_32_bits(virtual));
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/include/nvkm/core/ |
| os.h | 35 iowrite32_native(lower_32_bits(_v), &_p[0]); \
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/pmu/ |
| nouveau_nvkm_subdev_pmu_gm20b.c | 88 hdr.code_dma_base = lower_32_bits((addr + adjust) >> 8);
91 hdr.data_dma_base = lower_32_bits((addr + adjust) >> 8);
94 hdr.overlay_dma_base = lower_32_bits((addr + adjust) << 8);
110 .code_dma_base = lower_32_bits(code),
114 .data_dma_base = lower_32_bits(data),
116 .overlay_dma_base = lower_32_bits(code),
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_vcn_v2_5.c | 409 lower_32_bits(adev->vcn.inst[i].gpu_addr));
420 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset));
428 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
464 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
485 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
505 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
873 lower_32_bits(ring->gpu_addr));
884 lower_32_bits(ring->wptr));
1046 lower_32_bits(ring->gpu_addr));
1055 lower_32_bits(ring->wptr))
[all...] |
| amdgpu_sdma_v2_4.c | 232 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2);
264 sdma_v2_4_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
269 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
320 amdgpu_ring_write(ring, lower_32_bits(addr));
322 amdgpu_ring_write(ring, lower_32_bits(seq));
328 amdgpu_ring_write(ring, lower_32_bits(addr));
464 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
472 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2);
576 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
629 ib.ptr[1] = lower_32_bits(gpu_addr)
[all...] |
| amdgpu_vcn_v2_0.c | 324 lower_32_bits(adev->vcn.inst->gpu_addr));
336 lower_32_bits(adev->vcn.inst->gpu_addr + offset));
344 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
381 lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
402 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);
422 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
860 lower_32_bits(ring->gpu_addr));
871 lower_32_bits(ring->wptr));
1014 lower_32_bits(ring->gpu_addr));
1023 lower_32_bits(ring->wptr))
[all...] |
| amdgpu_vcn_v1_0.c | 312 lower_32_bits(adev->vcn.inst->gpu_addr));
324 lower_32_bits(adev->vcn.inst->gpu_addr + offset));
332 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
382 lower_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0);
394 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0);
404 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
924 lower_32_bits(ring->gpu_addr));
935 lower_32_bits(ring->wptr));
941 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
942 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr))
[all...] |
| amdgpu_si_dma.c | 65 (lower_32_bits(ring->wptr) << 2) & 0x3fffc);
77 while ((lower_32_bits(ring->wptr) & 7) != 5)
163 WREG32(DMA_RB_RPTR_ADDR_LO + sdma_offsets[i], lower_32_bits(rptr_addr));
182 WREG32(DMA_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2);
229 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
280 ib.ptr[1] = lower_32_bits(gpu_addr);
327 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
328 ib->ptr[ib->length_dw++] = lower_32_bits(src);
351 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
354 ib->ptr[ib->length_dw++] = lower_32_bits(value)
[all...] |
| amdgpu_vce_v4_0.c | 115 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
116 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
122 lower_32_bits(ring->wptr));
125 lower_32_bits(ring->wptr));
128 lower_32_bits(ring->wptr));
170 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO), lower_32_bits(addr));
241 lower_32_bits(ring->gpu_addr));
349 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR), lower_32_bits(ring->wptr));
350 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR), lower_32_bits(ring->wptr));
357 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR2), lower_32_bits(ring->wptr))
[all...] |
| amdgpu_sdma_v5_0.c | 244 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
337 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
340 lower_32_bits(ring->wptr << 2),
343 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2);
353 lower_32_bits(ring->wptr << 2),
357 lower_32_bits(ring->wptr << 2));
400 sdma_v5_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
405 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
408 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
461 amdgpu_ring_write(ring, lower_32_bits(addr))
[all...] |
| amdgpu_cik_sdma.c | 203 (lower_32_bits(ring->wptr) << 2) & 0x3fffc);
236 cik_sdma_ring_insert_nop(ring, (4 - lower_32_bits(ring->wptr)) & 7);
287 amdgpu_ring_write(ring, lower_32_bits(addr));
289 amdgpu_ring_write(ring, lower_32_bits(seq));
295 amdgpu_ring_write(ring, lower_32_bits(addr));
493 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2);
640 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
693 ib.ptr[1] = lower_32_bits(gpu_addr);
743 ib->ptr[ib->length_dw++] = lower_32_bits(src);
745 ib->ptr[ib->length_dw++] = lower_32_bits(pe)
[all...] |
| amdgpu_vce_v2_0.c | 99 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
101 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
249 WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr));
250 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
256 WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr));
257 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
|
| amdgpu_sdma_v3_0.c | 398 WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2));
399 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr) << 2);
403 WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2));
405 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2);
438 sdma_v3_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
443 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
494 amdgpu_ring_write(ring, lower_32_bits(addr));
496 amdgpu_ring_write(ring, lower_32_bits(seq));
502 amdgpu_ring_write(ring, lower_32_bits(addr));
703 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/dma/ |
| nouveau_nvkm_engine_dma_usergv100.c | 56 nvkm_wo32(*pgpuobj, 0x04, lower_32_bits(start));
58 nvkm_wo32(*pgpuobj, 0x0c, lower_32_bits(limit));
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/fifo/ |
| nouveau_nvkm_engine_fifo_dmag84.c | 73 nvkm_wo32(chan->ramfc, 0x08, lower_32_bits(args->v0.offset));
75 nvkm_wo32(chan->ramfc, 0x10, lower_32_bits(args->v0.offset));
|
| nouveau_nvkm_engine_fifo_dmanv50.c | 73 nvkm_wo32(chan->ramfc, 0x08, lower_32_bits(args->v0.offset));
75 nvkm_wo32(chan->ramfc, 0x10, lower_32_bits(args->v0.offset));
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/gr/ |
| nouveau_nvkm_engine_gr_gm20b.c | 46 hdr.code_dma_base = lower_32_bits((addr + adjust) >> 8);
49 hdr.data_dma_base = lower_32_bits((addr + adjust) >> 8);
65 .code_dma_base = lower_32_bits(code),
69 .data_dma_base = lower_32_bits(data),
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_si_dma.c | 86 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
87 ib->ptr[ib->length_dw++] = lower_32_bits(src);
269 radeon_ring_write(ring, lower_32_bits(dst_offset));
270 radeon_ring_write(ring, lower_32_bits(src_offset));
|
