| /src/sys/arch/sparc64/include/ |
| trap.h | 122 #define T_GETCC 0x132
|
| /src/sys/arch/amiga/amiga/ |
| cc_registers.h | 179 #define R_SPR4PTL 0x132
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| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_doorbell.h | 133 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5 = 0x132,
|
| ppsmc.h | 123 #define PPSMC_MSG_MCLKDPM_NoForcedLevel ((uint16_t) 0x132)
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| ppsmc.h | 120 #define PPSMC_MSG_MCLKDPM_NoForcedLevel ((uint16_t) 0x132)
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| omap4-var-om44customboard.dtsi | 74 OMAP4_IOPAD(0x132, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */
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| omap4-sdp.dts | 278 OMAP4_IOPAD(0x132, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */
|
| qcom-apq8060-dragonboard.dts | 427 reg = <0x132>;
|
| /src/lib/libform/ |
| form.h | 156 #define REQ_SCR_BCHAR (KEY_MAX + 0x132) /* horizontal scroll
|
| /src/sys/arch/sparc64/sparc64/ |
| hvcall.S | 129 #define RNG_CTL_WRITE 0x132
|
| locore.s | 821 STRAP(0x130); STRAP(0x131); STRAP(0x132); STRAP(0x133); STRAP(0x134); STRAP(0x135); STRAP(0x136); STRAP(0x137)
1032 STRAP(0x130); STRAP(0x131); STRAP(0x132); STRAP(0x133); STRAP(0x134); STRAP(0x135); STRAP(0x136); STRAP(0x137)
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/ |
| fiji_ppsmc.h | 228 #define PPSMC_MSG_MCLKDPM_NoForcedLevel ((uint16_t) 0x132)
|
| smu7_ppsmc.h | 225 #define PPSMC_MSG_MCLKDPM_NoForcedLevel ((uint16_t) 0x132)
|
| tonga_ppsmc.h | 252 #define PPSMC_MSG_MCLKDPM_NoForcedLevel ((uint16_t) 0x132)
|
| /src/sys/external/gpl2/dts/dist/include/dt-bindings/input/ |
| linux-event-codes.h | 386 #define BTN_C 0x132
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gmc/ |
| gmc_7_1_d.h | 1207 #define ixMC_IO_DEBUG_DQB1L_TXPHASE_D1 0x132
|
| gmc_8_1_d.h | 1311 #define ixMC_IO_DEBUG_DQB1L_TXPHASE_D1 0x132
|
| /src/sys/dev/microcode/aic7xxx/ |
| aic79xx_reg.h | 2021 ahd_print_register(NULL, 0, "DMAPARAMS", 0x132, regvalue, cur_col, wrap)
3533 #define DMAPARAMS 0x132
|
| /src/sys/external/bsd/drm2/dist/drm/ast/ |
| ast_post.c | 1085 param->dram_config = 0x132;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/ |
| gfx_8_0_enum.h | 434 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2= 0x132,
1634 SC_PA0_SC_EVENT_WE = 0x132,
|
| gfx_8_1_enum.h | 434 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2= 0x132,
1652 SC_PA0_SC_EVENT_WE = 0x132,
|
| gfx_7_2_enum.h | 1449 SC_PA0_SC_EVENT_WE = 0x132,
|
| /src/sys/lib/libkern/arch/hppa/ |
| milli.S | 1347 x132: sh3add %r26,0,%r1 ! sh2add %r1,%r26,%r1 ! b e_shift ! sh2add %r1,%r29,%r29 label
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/device/ |
| nouveau_nvkm_engine_device_base.c | 3193 case 0x132: device->chip = &nv132_chipset; break;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/ |
| dce_8_0_d.h | 1038 #define mmLIGHT_SLEEP_CNTL 0x132
|
