Searched refs:wave (Results 1 - 22 of 22) sorted by relevance

/xsrc/external/mit/mesa-demos/dist/src/samples/
H A DMakefile.am62 wave
H A DMakefile.in125 @HAVE_GLUT_TRUE@ wave$(EXEEXT)
224 wave_SOURCES = wave.c
225 wave_OBJECTS = wave.$(OBJEXT)
264 sphere.c star.c stencil.c stretch.c texture.c tri.c wave.c
268 sphere.c star.c stencil.c stretch.c texture.c tri.c wave.c
619 wave$(EXEEXT): $(wave_OBJECTS) $(wave_DEPENDENCIES) $(EXTRA_wave_DEPENDENCIES)
620 @rm -f wave$(EXEEXT)
656 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/wave.Po@am__quote@
/xsrc/external/mit/MesaLib.old/dist/src/amd/common/
H A Dac_debug.h44 unsigned wave; member in struct:ac_wave_info
50 bool matched; /* whether the wave is used by a currently-bound shader */
H A Dac_debug.c752 if (w1->wave < w2->wave)
754 if (w1->wave > w2->wave)
760 /* Return wave information. "waves" should be a large enough array. */
784 &w->se, &w->sh, &w->cu, &w->simd, &w->wave,
/xsrc/external/mit/MesaLib/dist/src/amd/common/
H A Dac_debug.h48 unsigned wave; member in struct:ac_wave_info
54 bool matched; /* whether the wave is used by a currently-bound shader */
H A Dac_debug.c791 if (w1->wave < w2->wave)
793 if (w1->wave > w2->wave)
799 /* Return wave information. "waves" should be a large enough array. */
828 &w->wave, &w->status, &pc_hi, &pc_lo, &w->inst_dw0, &w->inst_dw1, &exec_hi,
/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
H A Dradv_debug.c386 /* See if any wave executes the shader. */
395 /* Remember the first found wave. The waves are sorted according to PC. */
424 waves->wave, waves->exec);
478 waves[i].wave, waves[i].exec, waves[i].inst_dw0,
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D13.0.3.rst106 - radeonsi: apply a multi-wave workgroup SPI bug workaround to affected
H A D20.1.6.rst109 - radeonsi: use correct wave size in gfx10_ngg_calculate_subgroup_info
H A D19.2.0.rst346 - radeonsi/gfx10: fix wave occupancy computations
H A D20.0.0.rst3407 - aco/wave32: Replace hardcoded numbers in spiller with wave size.
3408 - aco/wave32: Introduce emit_mbcnt which takes wave size into account.
3409 - aco/wave32: Add wave size specific opcodes to aco_builder.
H A D20.3.0.rst3310 - radeonsi: use correct wave size in gfx10_ngg_calculate_subgroup_info
3454 - radeonsi: add a tweak for PS wave CU utilization for gfx10.3
4325 - radv: add a tweak for PS wave CU utilization for gfx10.3
4516 - aco: Optimize thread_id_in_threadgroup when there is just one wave.
4517 - aco: Add wave-specific opcode for s_lshl and s_flbit.
H A D20.1.0.rst3121 - radeonsi/gfx10: fix the wave size for compute-based culling
4204 - aco: Skip 2nd read of merged wave info when TCS in/out vertices are
4239 - aco: Use 24-bit multiplication for NGG wave id and thread id.
H A D21.3.0.rst3467 - radeonsi/sqtt: export wave size and scratch size
3872 - ac/rgp, radv: report wave size for shaders
4123 - ac/nir: Don't count vertices and primitives in wave after culling.
H A D21.2.0.rst1440 - ir3: Only use per-wave pvtmem layout for compute
4974 - radv: Ignore GS copy shader when determining NGG GS wave size.
5034 - ac/nir: Use a ballot that matches the wave size during NGG lowering.
H A D20.2.0.rst3240 - radeonsi: compute perf tests - don't test 1 wave/SA limit, test no limit first
3388 - radeonsi: use correct wave size in gfx10_ngg_calculate_subgroup_info
H A D19.3.0.rst2353 - radeonsi/gfx10: fix wave occupancy computations
/xsrc/external/mit/MesaLib/dist/src/amd/compiler/
H A DREADME.md17 In case of GCN / RDNA the parallelism is achieved by executing the shader on several waves, and each wave has several lanes (32 or 64).
85 Scheduling is another NP-complete problem where basically all known heuristics suffer from unpredictable change in register pressure. For that reason, the implemented scheduler does not completely re-schedule all instructions, but only aims to move up memory loads as far as possible without exceeding the maximum register limit for the pre-calculated wave count. The reason this works is that ILP is very limited on GCN. This approach looks promising so far.
89 The register allocator works on SSA (as opposed to LLVM's which works on virtual registers). The SSA properties guarantee that there are always as many registers available as needed. The problem is that some instructions require a vector of neighboring registers to be available, but the free regs might be scattered. In this case, the register allocator inserts shuffle code (moving some temporaries to other registers) to make space for the variable. The assumption is that it is (almost) always better to have a few more moves than to sacrifice a wave. The RA does SSA-reconstruction on the fly, which makes its runtime linear.
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_debug.c312 /* See if any wave executes the shader. */
321 /* Remember the first found wave. The waves are sorted according to PC. */
348 waves->se, waves->sh, waves->cu, waves->simd, waves->wave, waves->exec);
398 waves[i].se, waves[i].sh, waves[i].cu, waves[i].simd, waves[i].wave, waves[i].exec,
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_debug.c926 /* See if any wave executes the shader. */
934 /* Remember the first found wave. The waves are sorted according to PC. */
981 waves->wave, waves->exec);
1031 waves[i].wave, waves[i].exec, waves[i].inst_dw0,
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_debug.c911 /* See if any wave executes the shader. */
919 /* Remember the first found wave. The waves are sorted according to PC. */
967 waves->se, waves->sh, waves->cu, waves->simd, waves->wave, waves->exec);
1014 waves[i].se, waves[i].sh, waves[i].cu, waves[i].simd, waves[i].wave, waves[i].exec,
/xsrc/external/mit/MesaLib/dist/
H A D.pick_status.json26806 "description": "radeonsi: centralize wave size computation in si_get_shader_wave_size",
30262 "description": "aco: optimize load_local_invocation_index with single-wave workgroups",
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