1 ; Options for the DEC Alpha port of the compiler 2 ; 3 ; Copyright (C) 2005-2022 Free Software Foundation, Inc. 4 ; 5 ; This file is part of GCC. 6 ; 7 ; GCC is free software; you can redistribute it and/or modify it under 8 ; the terms of the GNU General Public License as published by the Free 9 ; Software Foundation; either version 3, or (at your option) any later 10 ; version. 11 ; 12 ; GCC is distributed in the hope that it will be useful, but WITHOUT 13 ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 ; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 ; License for more details. 16 ; 17 ; You should have received a copy of the GNU General Public License 18 ; along with GCC; see the file COPYING3. If not see 19 ; <http://www.gnu.org/licenses/>. 20 21 msoft-float 22 Target Mask(SOFT_FP) 23 Do not use hardware fp. 24 25 mfp-regs 26 Target Mask(FPREGS) 27 Use fp registers. 28 29 mgas 30 Target Ignore 31 Does nothing. Preserved for backward compatibility. 32 33 mieee-conformant 34 Target RejectNegative Mask(IEEE_CONFORMANT) 35 Request IEEE-conformant math library routines (OSF/1). 36 37 mieee 38 Target RejectNegative Mask(IEEE) 39 Emit IEEE-conformant code, without inexact exceptions. 40 41 mieee-with-inexact 42 Target RejectNegative Mask(IEEE_WITH_INEXACT) 43 44 mbuild-constants 45 Target Mask(BUILD_CONSTANTS) 46 Do not emit complex integer constants to read-only memory. 47 48 mfloat-vax 49 Target RejectNegative Mask(FLOAT_VAX) 50 Use VAX fp. 51 52 mfloat-ieee 53 Target RejectNegative InverseMask(FLOAT_VAX) 54 Do not use VAX fp. 55 56 mbwx 57 Target Mask(BWX) 58 Emit code for the byte/word ISA extension. 59 60 mmax 61 Target Mask(MAX) 62 Emit code for the motion video ISA extension. 63 64 mfix 65 Target Mask(FIX) 66 Emit code for the fp move and sqrt ISA extension. 67 68 mcix 69 Target Mask(CIX) 70 Emit code for the counting ISA extension. 71 72 mexplicit-relocs 73 Target Mask(EXPLICIT_RELOCS) 74 Emit code using explicit relocation directives. 75 76 msmall-data 77 Target RejectNegative Mask(SMALL_DATA) 78 Emit 16-bit relocations to the small data areas. 79 80 mlarge-data 81 Target RejectNegative InverseMask(SMALL_DATA) 82 Emit 32-bit relocations to the small data areas. 83 84 msmall-text 85 Target RejectNegative Mask(SMALL_TEXT) 86 Emit direct branches to local functions. 87 88 mlarge-text 89 Target RejectNegative InverseMask(SMALL_TEXT) 90 Emit indirect branches to local functions. 91 92 mtls-kernel 93 Target Mask(TLS_KERNEL) 94 Emit rdval instead of rduniq for thread pointer. 95 96 mlong-double-128 97 Target RejectNegative Mask(LONG_DOUBLE_128) 98 Use 128-bit long double. 99 100 mlong-double-64 101 Target RejectNegative InverseMask(LONG_DOUBLE_128) 102 Use 64-bit long double. 103 104 mcpu= 105 Target RejectNegative Joined Var(alpha_cpu_string) 106 Use features of and schedule given CPU. 107 108 mtune= 109 Target RejectNegative Joined Var(alpha_tune_string) 110 Schedule given CPU. 111 112 mfp-rounding-mode= 113 Target RejectNegative Joined Var(alpha_fprm_string) 114 Control the generated fp rounding mode. 115 116 mfp-trap-mode= 117 Target RejectNegative Joined Var(alpha_fptm_string) 118 Control the IEEE trap mode. 119 120 mtrap-precision= 121 Target RejectNegative Joined Var(alpha_tp_string) 122 Control the precision given to fp exceptions. 123 124 mmemory-latency= 125 Target RejectNegative Joined Var(alpha_mlat_string) 126 Tune expected memory latency. 127 128 mtls-size= 129 Target RejectNegative Joined UInteger Var(alpha_tls_size) Init(32) 130 Specify bit size of immediate TLS offsets. 131