1 /* $NetBSD: tegra_reg.h,v 1.25 2018/04/01 04:35:04 ryo Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _ARM_TEGRA_REG_H 30 #define _ARM_TEGRA_REG_H 31 32 #define TEGRA_PCIE_OFFSET 0x01000000 33 #define TEGRA_PCIE_SIZE 0x3f000000 34 #define TEGRA_PCIE_RPCONF_BASE 0x01000000 35 #define TEGRA_PCIE_RPCONF_SIZE 0x00002000 36 #define TEGRA_PCIE_PADS_BASE 0x01003000 37 #define TEGRA_PCIE_PADS_SIZE 0x00000800 38 #define TEGRA_PCIE_AFI_BASE 0x01003800 39 #define TEGRA_PCIE_AFI_SIZE 0x00000800 40 #define TEGRA_PCIE_A1_BASE 0x01000000 41 #define TEGRA_PCIE_A1_SIZE 0x01000000 42 #define TEGRA_PCIE_A2_BASE 0x02000000 43 #define TEGRA_PCIE_A2_SIZE 0x0e000000 44 #define TEGRA_PCIE_A3_BASE 0x10000000 45 #define TEGRA_PCIE_A3_SIZE 0x30000000 46 47 #define TEGRA_PCIE_CONF_BASE 0x02000000 48 #define TEGRA_PCIE_CONF_SIZE 0x01000000 49 #define TEGRA_PCIE_IO_BASE 0x01800000 /* comment in tegra_pcie.c */ 50 #define TEGRA_PCIE_IO_SIZE 0x00800000 51 #define TEGRA_PCIE_MEM_BASE 0x03000000 52 #define TEGRA_PCIE_MEM_SIZE 0x0d000000 53 #define TEGRA_PCIE_EXTC_BASE 0x10000000 54 #define TEGRA_PCIE_EXTC_SIZE 0x10000000 55 #define TEGRA_PCIE_PMEM_BASE 0x20000000 56 #define TEGRA_PCIE_PMEM_SIZE 0x20000000 57 58 #define TEGRA_HOST1X_BASE 0x50000000 59 #define TEGRA_HOST1X_SIZE 0x00034000 60 #define TEGRA_GHOST_BASE 0x54000000 61 #define TEGRA_GHOST_SIZE 0x01000000 62 #define TEGRA_GPU_BASE 0x57000000 63 #define TEGRA_GPU_SIZE 0x02000000 64 #define TEGRA_PPSB_BASE 0x60000000 65 #define TEGRA_PPSB_SIZE 0x01000000 66 #define TEGRA_APB_BASE 0x70000000 67 #define TEGRA_APB_SIZE 0x01000000 68 #define TEGRA_AHB_A2_BASE 0x7c000000 69 #define TEGRA_AHB_A2_SIZE 0x02000000 70 71 /* APB */ 72 #define TEGRA_MPIO_OFFSET 0x00000000 73 #define TEGRA_MPIO_SIZE 0x4000 74 #define TEGRA_UARTA_OFFSET 0x00006000 75 #define TEGRA_UARTA_SIZE 0x40 76 #define TEGRA_UARTB_OFFSET 0x00006040 77 #define TEGRA_UARTB_SIZE 0x40 78 #define TEGRA_UARTC_OFFSET 0x00006200 79 #define TEGRA_UARTC_SIZE 0x100 80 #define TEGRA_UARTD_OFFSET 0x00006300 81 #define TEGRA_UARTD_SIZE 0x100 82 #define TEGRA_I2C1_OFFSET 0x0000c000 83 #define TEGRA_I2C1_SIZE 0x100 84 #define TEGRA_I2C2_OFFSET 0x0000c400 85 #define TEGRA_I2C2_SIZE 0x100 86 #define TEGRA_I2C3_OFFSET 0x0000c500 87 #define TEGRA_I2C3_SIZE 0x100 88 #define TEGRA_I2C4_OFFSET 0x0000c700 89 #define TEGRA_I2C4_SIZE 0x100 90 #define TEGRA_I2C5_OFFSET 0x0000d000 91 #define TEGRA_I2C5_SIZE 0x100 92 #define TEGRA_I2C6_OFFSET 0x0000d100 93 #define TEGRA_I2C6_SIZE 0x100 94 #define TEGRA_RTC_OFFSET 0x0000e000 95 #define TEGRA_RTC_SIZE 0x100 96 #define TEGRA_KBC_OFFSET 0x0000e200 97 #define TEGRA_KBC_SIZE 0x100 98 #define TEGRA_PMC_OFFSET 0x0000e400 99 #define TEGRA_PMC_SIZE 0x800 100 #define TEGRA_FUSE_OFFSET 0x0000f800 101 #define TEGRA_FUSE_SIZE 0x00000400 102 #define TEGRA_CEC_OFFSET 0x00015000 103 #define TEGRA_CEC_SIZE 0x1000 104 #define TEGRA_MC_OFFSET 0x00019000 105 #define TEGRA_MC_SIZE 0x1000 106 #define TEGRA_SATA_OFFSET 0x00020000 107 #define TEGRA_SATA_SIZE 0x10000 108 #define TEGRA_HDA_OFFSET 0x00030000 109 #define TEGRA_HDA_SIZE 0x10000 110 #define TEGRA_XUSB_PADCTL_OFFSET 0x0009f000 111 #define TEGRA_XUSB_PADCTL_SIZE 0x1000 112 #define TEGRA_XUSB_HOST_OFFSET 0x00090000 113 #define TEGRA_XUSB_HOST_SIZE 0xa000 114 #define TEGRA_SDMMC1_OFFSET 0x000b0000 115 #define TEGRA_SDMMC1_SIZE 0x200 116 #define TEGRA_SDMMC2_OFFSET 0x000b0200 117 #define TEGRA_SDMMC2_SIZE 0x200 118 #define TEGRA_SDMMC3_OFFSET 0x000b0400 119 #define TEGRA_SDMMC3_SIZE 0x200 120 #define TEGRA_SDMMC4_OFFSET 0x000b0600 121 #define TEGRA_SDMMC4_SIZE 0x200 122 #define TEGRA_XUSB_DEV_OFFSET 0x000d0000 123 #define TEGRA_XUSB_DEV_SIZE 0xa000 124 #define TEGRA_SOC_THERM_OFFSET 0x000e2000 125 #define TEGRA_SOC_THERM_SIZE 0x1000 126 127 /* PPSB */ 128 #define TEGRA_TIMER_OFFSET 0x00005000 129 #define TEGRA_TIMER_SIZE 0x400 130 #define TEGRA_CAR_OFFSET 0x00006000 131 #define TEGRA_CAR_SIZE 0x1000 132 #define TEGRA_GPIO_OFFSET 0x0000d000 133 #define TEGRA_GPIO_SIZE 0x00000800 134 #define TEGRA_EVP_OFFSET 0x0000f000 135 #define TEGRA_EVP_SIZE 0x1000 136 137 /* AHB_A2 */ 138 #define TEGRA_USB1_OFFSET 0x01000000 139 #define TEGRA_USB1_SIZE 0x1800 140 #define TEGRA_USB2_OFFSET 0x01004000 141 #define TEGRA_USB2_SIZE 0x1800 142 #define TEGRA_USB3_OFFSET 0x01008000 143 #define TEGRA_USB3_SIZE 0x1800 144 145 /* Graphics Host (GHOST) */ 146 #define TEGRA_DISPLAYA_OFFSET 0x00200000 147 #define TEGRA_DISPLAYA_SIZE 0x00040000 148 #define TEGRA_DISPLAYB_OFFSET 0x00240000 149 #define TEGRA_DISPLAYB_SIZE 0x00040000 150 #define TEGRA_HDMI_OFFSET 0x00280000 151 #define TEGRA_HDMI_SIZE 0x00040000 152 #define TEGRA_SOR_OFFSET 0x00540000 153 #define TEGRA_SOR_SIZE 0x00040000 154 #define TEGRA_DPAUX_OFFSET 0x005c0000 155 #define TEGRA_DPAUX_SIZE 0x00040000 156 157 #endif /* _ARM_TEGRA_REG_H */ 158
Indexes created Tue Sep 23 07:09:52 GMT 2025