tegra_reg.h revision 1.1.2.3
1 1.1.2.3 skrll /* $NetBSD: tegra_reg.h,v 1.1.2.3 2015/06/06 14:39:56 skrll Exp $ */ 2 1.1.2.2 skrll 3 1.1.2.2 skrll /*- 4 1.1.2.2 skrll * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 1.1.2.2 skrll * All rights reserved. 6 1.1.2.2 skrll * 7 1.1.2.2 skrll * Redistribution and use in source and binary forms, with or without 8 1.1.2.2 skrll * modification, are permitted provided that the following conditions 9 1.1.2.2 skrll * are met: 10 1.1.2.2 skrll * 1. Redistributions of source code must retain the above copyright 11 1.1.2.2 skrll * notice, this list of conditions and the following disclaimer. 12 1.1.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 13 1.1.2.2 skrll * notice, this list of conditions and the following disclaimer in the 14 1.1.2.2 skrll * documentation and/or other materials provided with the distribution. 15 1.1.2.2 skrll * 16 1.1.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 1.1.2.2 skrll * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 1.1.2.2 skrll * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 1.1.2.2 skrll * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 1.1.2.2 skrll * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 1.1.2.2 skrll * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 1.1.2.2 skrll * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 1.1.2.2 skrll * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 1.1.2.2 skrll * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 1.1.2.2 skrll * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 1.1.2.2 skrll * SUCH DAMAGE. 27 1.1.2.2 skrll */ 28 1.1.2.2 skrll 29 1.1.2.2 skrll #ifndef _ARM_TEGRA_REG_H 30 1.1.2.2 skrll #define _ARM_TEGRA_REG_H 31 1.1.2.2 skrll 32 1.1.2.2 skrll #define CONSADDR_VA (CONSADDR - TEGRA_APB_BASE + TEGRA_APB_VBASE) 33 1.1.2.2 skrll 34 1.1.2.2 skrll #define TEGRA_EXTMEM_BASE 0x80000000 35 1.1.2.2 skrll 36 1.1.2.3 skrll #define TEGRA_PCIE_OFFSET 0x01000000 37 1.1.2.3 skrll #define TEGRA_PCIE_SIZE 0x3effffff 38 1.1.2.3 skrll #define TEGRA_PCIE_PADS_BASE 0x01003000 39 1.1.2.3 skrll #define TEGRA_PCIE_PADS_SIZE 0x00000800 40 1.1.2.3 skrll #define TEGRA_PCIE_AFI_BASE 0x01003800 41 1.1.2.3 skrll #define TEGRA_PCIE_AFI_SIZE 0x00000800 42 1.1.2.3 skrll #define TEGRA_PCIE_A1_BASE 0x01000000 43 1.1.2.3 skrll #define TEGRA_PCIE_A1_SIZE 0x00002000 44 1.1.2.3 skrll #define TEGRA_PCIE_A2_BASE 0x02000000 45 1.1.2.3 skrll #define TEGRA_PCIE_A2_SIZE 0x01000000 46 1.1.2.3 skrll 47 1.1.2.3 skrll #define TEGRA_PCIE_IO_BASE 0x12000000 48 1.1.2.3 skrll #define TEGRA_PCIE_IO_SIZE 0x00010000 49 1.1.2.3 skrll #define TEGRA_PCIE_MEM_BASE 0x13000000 50 1.1.2.3 skrll #define TEGRA_PCIE_MEM_SIZE 0x0d000000 51 1.1.2.3 skrll #define TEGRA_PCIE_PMEM_BASE 0x20000000 52 1.1.2.3 skrll #define TEGRA_PCIE_PMEM_SIZE 0x20000000 53 1.1.2.3 skrll 54 1.1.2.2 skrll #define TEGRA_HOST1X_BASE 0x50000000 55 1.1.2.3 skrll #define TEGRA_HOST1X_SIZE 0x00034000 56 1.1.2.3 skrll #define TEGRA_GHOST_BASE 0x54000000 57 1.1.2.3 skrll #define TEGRA_GHOST_SIZE 0x01000000 58 1.1.2.2 skrll #define TEGRA_PPSB_BASE 0x60000000 59 1.1.2.2 skrll #define TEGRA_PPSB_SIZE 0x01000000 60 1.1.2.2 skrll #define TEGRA_APB_BASE 0x70000000 61 1.1.2.2 skrll #define TEGRA_APB_SIZE 0x01000000 62 1.1.2.2 skrll #define TEGRA_AHB_A2_BASE 0x7c000000 63 1.1.2.2 skrll #define TEGRA_AHB_A2_SIZE 0x02000000 64 1.1.2.2 skrll 65 1.1.2.3 skrll #define TEGRA_HOST1X_VBASE 0xfaf00000 66 1.1.2.3 skrll #define TEGRA_PPSB_VBASE 0xfb000000 67 1.1.2.3 skrll #define TEGRA_APB_VBASE 0xfc000000 68 1.1.2.3 skrll #define TEGRA_AHB_A2_VBASE 0xfd000000 69 1.1.2.2 skrll 70 1.1.2.2 skrll #define TEGRA_REF_FREQ 12000000 71 1.1.2.2 skrll 72 1.1.2.2 skrll /* APB */ 73 1.1.2.3 skrll #define TEGRA_MPIO_OFFSET 0x00000000 74 1.1.2.3 skrll #define TEGRA_MPIO_SIZE 0x4000 75 1.1.2.2 skrll #define TEGRA_UARTA_OFFSET 0x00006000 76 1.1.2.2 skrll #define TEGRA_UARTA_SIZE 0x40 77 1.1.2.2 skrll #define TEGRA_UARTB_OFFSET 0x00006040 78 1.1.2.2 skrll #define TEGRA_UARTB_SIZE 0x40 79 1.1.2.2 skrll #define TEGRA_UARTC_OFFSET 0x00006200 80 1.1.2.2 skrll #define TEGRA_UARTC_SIZE 0x100 81 1.1.2.2 skrll #define TEGRA_UARTD_OFFSET 0x00006300 82 1.1.2.2 skrll #define TEGRA_UARTD_SIZE 0x100 83 1.1.2.3 skrll #define TEGRA_I2C1_OFFSET 0x0000c000 84 1.1.2.3 skrll #define TEGRA_I2C1_SIZE 0x100 85 1.1.2.3 skrll #define TEGRA_I2C2_OFFSET 0x0000c400 86 1.1.2.3 skrll #define TEGRA_I2C2_SIZE 0x100 87 1.1.2.3 skrll #define TEGRA_I2C3_OFFSET 0x0000c500 88 1.1.2.3 skrll #define TEGRA_I2C3_SIZE 0x100 89 1.1.2.3 skrll #define TEGRA_I2C4_OFFSET 0x0000c700 90 1.1.2.3 skrll #define TEGRA_I2C4_SIZE 0x100 91 1.1.2.3 skrll #define TEGRA_I2C5_OFFSET 0x0000d000 92 1.1.2.3 skrll #define TEGRA_I2C5_SIZE 0x100 93 1.1.2.3 skrll #define TEGRA_I2C6_OFFSET 0x0000d100 94 1.1.2.3 skrll #define TEGRA_I2C6_SIZE 0x100 95 1.1.2.2 skrll #define TEGRA_RTC_OFFSET 0x0000e000 96 1.1.2.2 skrll #define TEGRA_RTC_SIZE 0x100 97 1.1.2.2 skrll #define TEGRA_KBC_OFFSET 0x0000e200 98 1.1.2.2 skrll #define TEGRA_KBC_SIZE 0x100 99 1.1.2.2 skrll #define TEGRA_PMC_OFFSET 0x0000e400 100 1.1.2.2 skrll #define TEGRA_PMC_SIZE 0x800 101 1.1.2.2 skrll #define TEGRA_MC_OFFSET 0x00019000 102 1.1.2.2 skrll #define TEGRA_MC_SIZE 0x1000 103 1.1.2.2 skrll #define TEGRA_SATA_OFFSET 0x00020000 104 1.1.2.2 skrll #define TEGRA_SATA_SIZE 0x10000 105 1.1.2.2 skrll #define TEGRA_HDA_OFFSET 0x00030000 106 1.1.2.2 skrll #define TEGRA_HDA_SIZE 0x10000 107 1.1.2.2 skrll #define TEGRA_XUSB_PADCTL_OFFSET 0x0009f000 108 1.1.2.2 skrll #define TEGRA_XUSB_PADCTL_SIZE 0x1000 109 1.1.2.2 skrll #define TEGRA_XUSB_HOST_OFFSET 0x00090000 110 1.1.2.2 skrll #define TEGRA_XUSB_HOST_SIZE 0xa000 111 1.1.2.2 skrll #define TEGRA_SDMMC1_OFFSET 0x000b0000 112 1.1.2.2 skrll #define TEGRA_SDMMC1_SIZE 0x200 113 1.1.2.2 skrll #define TEGRA_SDMMC2_OFFSET 0x000b0200 114 1.1.2.2 skrll #define TEGRA_SDMMC2_SIZE 0x200 115 1.1.2.2 skrll #define TEGRA_SDMMC3_OFFSET 0x000b0400 116 1.1.2.2 skrll #define TEGRA_SDMMC3_SIZE 0x200 117 1.1.2.2 skrll #define TEGRA_SDMMC4_OFFSET 0x000b0600 118 1.1.2.2 skrll #define TEGRA_SDMMC4_SIZE 0x200 119 1.1.2.2 skrll #define TEGRA_XUSB_DEV_OFFSET 0x000d0000 120 1.1.2.2 skrll #define TEGRA_XUSB_DEV_SIZE 0xa000 121 1.1.2.2 skrll 122 1.1.2.3 skrll /* PPSB */ 123 1.1.2.3 skrll #define TEGRA_TIMER_OFFSET 0x00005000 124 1.1.2.3 skrll #define TEGRA_TIMER_SIZE 0x400 125 1.1.2.3 skrll #define TEGRA_CAR_OFFSET 0x00006000 126 1.1.2.3 skrll #define TEGRA_CAR_SIZE 0x1000 127 1.1.2.3 skrll #define TEGRA_GPIO_OFFSET 0x0000d000 128 1.1.2.3 skrll #define TEGRA_GPIO_SIZE 0x00000800 129 1.1.2.3 skrll #define TEGRA_EVP_OFFSET 0x0000f000 130 1.1.2.3 skrll #define TEGRA_EVP_SIZE 0x1000 131 1.1.2.3 skrll 132 1.1.2.2 skrll /* AHB_A2 */ 133 1.1.2.2 skrll #define TEGRA_USB1_OFFSET 0x01000000 134 1.1.2.2 skrll #define TEGRA_USB1_SIZE 0x1800 135 1.1.2.2 skrll #define TEGRA_USB2_OFFSET 0x01004000 136 1.1.2.2 skrll #define TEGRA_USB2_SIZE 0x1800 137 1.1.2.2 skrll #define TEGRA_USB3_OFFSET 0x01008000 138 1.1.2.2 skrll #define TEGRA_USB3_SIZE 0x1800 139 1.1.2.2 skrll 140 1.1.2.3 skrll /* Graphics Host (GHOST) */ 141 1.1.2.3 skrll #define TEGRA_DISPLAYA_OFFSET 0x00200000 142 1.1.2.3 skrll #define TEGRA_DISPLAYA_SIZE 0x00040000 143 1.1.2.3 skrll #define TEGRA_DISPLAYB_OFFSET 0x00240000 144 1.1.2.3 skrll #define TEGRA_DISPLAYB_SIZE 0x00040000 145 1.1.2.3 skrll #define TEGRA_HDMI_OFFSET 0x00280000 146 1.1.2.3 skrll #define TEGRA_HDMI_SIZE 0x00040000 147 1.1.2.3 skrll 148 1.1.2.2 skrll #endif /* _ARM_TEGRA_REG_H */ 149
Indexes created Sun Oct 26 18:09:56 GMT 2025