tegra_reg.h revision 1.15
1 /* $NetBSD: tegra_reg.h,v 1.15 2015/11/14 02:00:42 jakllsch Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _ARM_TEGRA_REG_H 30 #define _ARM_TEGRA_REG_H 31 32 #define CONSADDR_VA (CONSADDR - TEGRA_APB_BASE + TEGRA_APB_VBASE) 33 34 #define TEGRA_EXTMEM_BASE 0x80000000 35 36 #define TEGRA_PCIE_OFFSET 0x01000000 37 #define TEGRA_PCIE_SIZE 0x3f000000 38 #define TEGRA_PCIE_PADS_BASE 0x01003000 39 #define TEGRA_PCIE_PADS_SIZE 0x00000800 40 #define TEGRA_PCIE_AFI_BASE 0x01003800 41 #define TEGRA_PCIE_AFI_SIZE 0x00000800 42 #define TEGRA_PCIE_A1_BASE 0x01000000 43 #define TEGRA_PCIE_A1_SIZE 0x00002000 44 #define TEGRA_PCIE_A2_BASE 0x02000000 45 #define TEGRA_PCIE_A2_SIZE 0x01000000 46 47 #define TEGRA_PCIE_IO_BASE 0x12000000 48 #define TEGRA_PCIE_IO_SIZE 0x00010000 49 #define TEGRA_PCIE_MEM_BASE 0x13000000 50 #define TEGRA_PCIE_MEM_SIZE 0x0d000000 51 #define TEGRA_PCIE_PMEM_BASE 0x20000000 52 #define TEGRA_PCIE_PMEM_SIZE 0x20000000 53 54 #define TEGRA_HOST1X_BASE 0x50000000 55 #define TEGRA_HOST1X_SIZE 0x00034000 56 #define TEGRA_GHOST_BASE 0x54000000 57 #define TEGRA_GHOST_SIZE 0x01000000 58 #define TEGRA_GPU_BASE 0x57000000 59 #define TEGRA_GPU_SIZE 0x02000000 60 #define TEGRA_PPSB_BASE 0x60000000 61 #define TEGRA_PPSB_SIZE 0x01000000 62 #define TEGRA_APB_BASE 0x70000000 63 #define TEGRA_APB_SIZE 0x01000000 64 #define TEGRA_AHB_A2_BASE 0x7c000000 65 #define TEGRA_AHB_A2_SIZE 0x02000000 66 67 #define TEGRA_HOST1X_VBASE 0xfaf00000 68 #define TEGRA_PPSB_VBASE 0xfb000000 69 #define TEGRA_APB_VBASE 0xfc000000 70 #define TEGRA_AHB_A2_VBASE 0xfd000000 71 72 #define TEGRA_REF_FREQ 12000000 73 74 /* APB */ 75 #define TEGRA_MPIO_OFFSET 0x00000000 76 #define TEGRA_MPIO_SIZE 0x4000 77 #define TEGRA_UARTA_OFFSET 0x00006000 78 #define TEGRA_UARTA_SIZE 0x40 79 #define TEGRA_UARTB_OFFSET 0x00006040 80 #define TEGRA_UARTB_SIZE 0x40 81 #define TEGRA_UARTC_OFFSET 0x00006200 82 #define TEGRA_UARTC_SIZE 0x100 83 #define TEGRA_UARTD_OFFSET 0x00006300 84 #define TEGRA_UARTD_SIZE 0x100 85 #define TEGRA_I2C1_OFFSET 0x0000c000 86 #define TEGRA_I2C1_SIZE 0x100 87 #define TEGRA_I2C2_OFFSET 0x0000c400 88 #define TEGRA_I2C2_SIZE 0x100 89 #define TEGRA_I2C3_OFFSET 0x0000c500 90 #define TEGRA_I2C3_SIZE 0x100 91 #define TEGRA_I2C4_OFFSET 0x0000c700 92 #define TEGRA_I2C4_SIZE 0x100 93 #define TEGRA_I2C5_OFFSET 0x0000d000 94 #define TEGRA_I2C5_SIZE 0x100 95 #define TEGRA_I2C6_OFFSET 0x0000d100 96 #define TEGRA_I2C6_SIZE 0x100 97 #define TEGRA_RTC_OFFSET 0x0000e000 98 #define TEGRA_RTC_SIZE 0x100 99 #define TEGRA_KBC_OFFSET 0x0000e200 100 #define TEGRA_KBC_SIZE 0x100 101 #define TEGRA_PMC_OFFSET 0x0000e400 102 #define TEGRA_PMC_SIZE 0x800 103 #define TEGRA_CEC_OFFSET 0x00015000 104 #define TEGRA_CEC_SIZE 0x1000 105 #define TEGRA_MC_OFFSET 0x00019000 106 #define TEGRA_MC_SIZE 0x1000 107 #define TEGRA_SATA_OFFSET 0x00020000 108 #define TEGRA_SATA_SIZE 0x10000 109 #define TEGRA_HDA_OFFSET 0x00030000 110 #define TEGRA_HDA_SIZE 0x10000 111 #define TEGRA_XUSB_PADCTL_OFFSET 0x0009f000 112 #define TEGRA_XUSB_PADCTL_SIZE 0x1000 113 #define TEGRA_XUSB_HOST_OFFSET 0x00090000 114 #define TEGRA_XUSB_HOST_SIZE 0xa000 115 #define TEGRA_SDMMC1_OFFSET 0x000b0000 116 #define TEGRA_SDMMC1_SIZE 0x200 117 #define TEGRA_SDMMC2_OFFSET 0x000b0200 118 #define TEGRA_SDMMC2_SIZE 0x200 119 #define TEGRA_SDMMC3_OFFSET 0x000b0400 120 #define TEGRA_SDMMC3_SIZE 0x200 121 #define TEGRA_SDMMC4_OFFSET 0x000b0600 122 #define TEGRA_SDMMC4_SIZE 0x200 123 #define TEGRA_XUSB_DEV_OFFSET 0x000d0000 124 #define TEGRA_XUSB_DEV_SIZE 0xa000 125 126 /* PPSB */ 127 #define TEGRA_TIMER_OFFSET 0x00005000 128 #define TEGRA_TIMER_SIZE 0x400 129 #define TEGRA_CAR_OFFSET 0x00006000 130 #define TEGRA_CAR_SIZE 0x1000 131 #define TEGRA_GPIO_OFFSET 0x0000d000 132 #define TEGRA_GPIO_SIZE 0x00000800 133 #define TEGRA_EVP_OFFSET 0x0000f000 134 #define TEGRA_EVP_SIZE 0x1000 135 136 /* AHB_A2 */ 137 #define TEGRA_USB1_OFFSET 0x01000000 138 #define TEGRA_USB1_SIZE 0x1800 139 #define TEGRA_USB2_OFFSET 0x01004000 140 #define TEGRA_USB2_SIZE 0x1800 141 #define TEGRA_USB3_OFFSET 0x01008000 142 #define TEGRA_USB3_SIZE 0x1800 143 144 /* Graphics Host (GHOST) */ 145 #define TEGRA_DISPLAYA_OFFSET 0x00200000 146 #define TEGRA_DISPLAYA_SIZE 0x00040000 147 #define TEGRA_DISPLAYB_OFFSET 0x00240000 148 #define TEGRA_DISPLAYB_SIZE 0x00040000 149 #define TEGRA_HDMI_OFFSET 0x00280000 150 #define TEGRA_HDMI_SIZE 0x00040000 151 #define TEGRA_SOR_OFFSET 0x00540000 152 #define TEGRA_SOR_SIZE 0x00040000 153 #define TEGRA_DPAUX_OFFSET 0x005c0000 154 #define TEGRA_DPAUX_SIZE 0x00040000 155 156 #endif /* _ARM_TEGRA_REG_H */ 157
Indexes created Wed Oct 01 07:09:59 GMT 2025