tegra_reg.h revision 1.2
1 /* $NetBSD: tegra_reg.h,v 1.2 2015/04/26 16:24:01 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _ARM_TEGRA_REG_H 30 #define _ARM_TEGRA_REG_H 31 32 #define CONSADDR_VA (CONSADDR - TEGRA_APB_BASE + TEGRA_APB_VBASE) 33 34 #define TEGRA_EXTMEM_BASE 0x80000000 35 36 #define TEGRA_HOST1X_BASE 0x50000000 37 #define TEGRA_HOST1X_SIZE 0x00100000 38 #define TEGRA_PPSB_BASE 0x60000000 39 #define TEGRA_PPSB_SIZE 0x01000000 40 #define TEGRA_APB_BASE 0x70000000 41 #define TEGRA_APB_SIZE 0x01000000 42 #define TEGRA_AHB_A2_BASE 0x7c000000 43 #define TEGRA_AHB_A2_SIZE 0x02000000 44 45 #define TEGRA_HOST1X_VBASE 0xfb000000 46 #define TEGRA_APB_VBASE 0xfc000000 47 #define TEGRA_AHB_A2_VBASE 0xfd000000 48 49 #define TEGRA_REF_FREQ 12000000 50 #define TEGRA_UART_FREQ TEGRA_REF_FREQ 51 52 /* APB */ 53 #define TEGRA_UARTA_OFFSET 0x00006000 54 #define TEGRA_UARTA_SIZE 0x40 55 #define TEGRA_UARTB_OFFSET 0x00006040 56 #define TEGRA_UARTB_SIZE 0x40 57 #define TEGRA_UARTC_OFFSET 0x00006200 58 #define TEGRA_UARTC_SIZE 0x100 59 #define TEGRA_UARTD_OFFSET 0x00006300 60 #define TEGRA_UARTD_SIZE 0x100 61 #define TEGRA_RTC_OFFSET 0x0000e000 62 #define TEGRA_RTC_SIZE 0x100 63 #define TEGRA_KBC_OFFSET 0x0000e200 64 #define TEGRA_KBC_SIZE 0x100 65 #define TEGRA_PMC_OFFSET 0x0000e400 66 #define TEGRA_PMC_SIZE 0x800 67 #define TEGRA_MC_OFFSET 0x00019000 68 #define TEGRA_MC_SIZE 0x1000 69 #define TEGRA_SATA_OFFSET 0x00020000 70 #define TEGRA_SATA_SIZE 0x10000 71 #define TEGRA_HDA_OFFSET 0x00030000 72 #define TEGRA_HDA_SIZE 0x10000 73 #define TEGRA_XUSB_PADCTL_OFFSET 0x0009f000 74 #define TEGRA_XUSB_PADCTL_SIZE 0x1000 75 #define TEGRA_XUSB_HOST_OFFSET 0x00090000 76 #define TEGRA_XUSB_HOST_SIZE 0xa000 77 #define TEGRA_SDMMC1_OFFSET 0x000b0000 78 #define TEGRA_SDMMC1_SIZE 0x200 79 #define TEGRA_SDMMC2_OFFSET 0x000b0200 80 #define TEGRA_SDMMC2_SIZE 0x200 81 #define TEGRA_SDMMC3_OFFSET 0x000b0400 82 #define TEGRA_SDMMC3_SIZE 0x200 83 #define TEGRA_SDMMC4_OFFSET 0x000b0600 84 #define TEGRA_SDMMC4_SIZE 0x200 85 #define TEGRA_XUSB_DEV_OFFSET 0x000d0000 86 #define TEGRA_XUSB_DEV_SIZE 0xa000 87 88 /* AHB_A2 */ 89 #define TEGRA_USB1_OFFSET 0x01000000 90 #define TEGRA_USB1_SIZE 0x1800 91 #define TEGRA_USB2_OFFSET 0x01004000 92 #define TEGRA_USB2_SIZE 0x1800 93 #define TEGRA_USB3_OFFSET 0x01008000 94 #define TEGRA_USB3_SIZE 0x1800 95 96 #endif /* _ARM_TEGRA_REG_H */ 97
Indexes created Mon Sep 29 21:09:56 GMT 2025