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      1 /* 	$NetBSD: temacreg.h,v 1.1 2006/12/02 22:18:47 freza Exp $ */
      2 
      3 /*
      4  * Copyright (c) 2006 Jachym Holecek
      5  * All rights reserved.
      6  *
      7  * Written for DFC Design, s.r.o.
      8  *
      9  * Redistribution and use in source and binary forms, with or without
     10  * modification, are permitted provided that the following conditions
     11  * are met:
     12  *
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  *
     16  * 2. Redistributions in binary form must reproduce the above copyright
     17  *    notice, this list of conditions and the following disclaimer in the
     18  *    documentation and/or other materials provided with the distribution.
     19  *
     20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     21  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     22  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     23  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     24  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     25  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     26  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     27  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     28  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     29  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #ifndef _VIRTEX_DEV_TEMACREG_H_
     33 #define _VIRTEX_DEV_TEMACREG_H_
     34 
     35 /*
     36  * Ethernet peripheral control (single register, see temac_control()).
     37  * This goes over normal DCR bus and is configured on EMAC block.
     38  */
     39 #define TEMAC_SIZE 		0x001c
     40 
     41 #define TEMAC_RESET 		0x0000
     42 #define TEMAC_RESET_PERIPH 	0x80000000 	/* Reset ethernet peripheral */
     43 #define TEMAC_RESET_EMAC 	0x40000000 	/* Reset EMAC core */
     44 #define TEMAC_RESET_PHY 	0x20000000 	/* Reset PHY core */
     45 
     46 /* LocalLink GMAC registers. Only ERRCNT implemented in temac. */
     47 #define TEMAC_GMAC_ERRCNT 	0x0018
     48 #define GMAC_ERR_FRAME(val) 	(((val) >> 16) & 0xffff)
     49 #define GMAC_ERR_OVERRUN(val) 	((val) & 0xffff)
     50 
     51 /*
     52  * Host interface ("GMI") registers, accessed indirectly via IDCR.
     53  */
     54 
     55 /* Pause frame address, bytes 0-3 */
     56 #define TEMAC_GMI_RXCF0 	0x0200 		/* Receiver conf word 0 */
     57 
     58 #define TEMAC_GMI_RXCF1 	0x0240 		/* Receiver conf word 1 */
     59 #define GMI_RX_RESET 		0x80000000 	/* Receiver reset */
     60 #define GMI_RX_JUMBO 		0x40000000 	/* Jumbo frame enable */
     61 #define GMI_RX_FCS 		0x20000000 	/* Pass FCS on Rx */
     62 #define GMI_RX_ENABLE 		0x10000000 	/* Enable receiver block */
     63 #define GMI_RX_VLAN 		0x08000000 	/* Receive VLAN tagged frames */
     64 #define GMI_RX_HDX 		0x04000000 	/* Half duplex Rx */
     65 #define GMI_RX_NOCHECK 		0x02000000 	/* Disable Length/Type check */
     66 #define GMI_RX_PAUSE_MASK 	0x0000ffff 	/* Pause frame addr 4-5 */
     67 
     68 #define TEMAC_GMI_TXCF 		0x0280 		/* Transmitter configuration */
     69 #define GMI_TX_RESET 		0x80000000 	/* Transmitter reset */
     70 #define GMI_TX_JUMBO 		0x40000000 	/* Jumbo frame enable */
     71 #define GMI_TX_FCS 		0x20000000 	/* Take FCS field from client */
     72 #define GMI_TX_ENABLE 		0x10000000 	/* Enable transmitter block */
     73 #define GMI_TX_VLAN 		0x08000000 	/* Transmit VLAN frames */
     74 #define GMI_TX_HDX 		0x04000000 	/* Half duplex Tx */
     75 #define GMI_TX_IFG 		0x02000000 	/* IFG adjustment enable */
     76 
     77 #define TEMAC_GMI_FLOWCF 	0x02c0 		/* Flow control configuration */
     78 #define GMI_FLOWCF_TX 		0x40000000 	/* Honor CLIENTEMAC#PAUSEREQ */
     79 #define GMI_FLOWCF_RX 		0x20000000 	/* HW pause frame handling */
     80 
     81 #define TEMAC_GMI_MMC 		0x0300 		/* MAC mode configuration */
     82 #define GMI_MMC_SPEED_MASK 	0xc0000000
     83 #define GMI_MMC_SPEED_NA 	0xc0000000
     84 #define GMI_MMC_SPEED_1000 	0x80000000
     85 #define GMI_MMC_SPEED_100 	0x40000000
     86 #define GMI_MMC_SPEED_10 	0x00000000
     87 #define GMI_MMC_RGMII 		0x20000000 	/* Enable RGMII mode */
     88 #define GMI_MMC_SGMII 		0x10000000 	/* Enable SGMII mode */
     89 #define GMI_MMC_1000BaseX 	0x08000000 	/* Enable 1000Base-X mode */
     90 #define GMI_MMC_HIE 		0x04000000 	/* Host interface enable */
     91 #define GMI_MMC_TX16 		0x02000000 	/* [1000BaseX] 16bit TX lane */
     92 #define GMI_MMC_RX16 		0x01000000 	/* [1000BaseX] 16bit RX lane */
     93 
     94 #define TEMAC_GMI_MGMTCF 	0x0340 		/* Management configuration */
     95 #define GMI_MGMT_CLKDIV_MASK 	0x0000003f 	/* MDIO clock divisor */
     96 #define GMI_MGMT_MDIO 		0x00000040 	/* MDIO link enable */
     97 
     98 /* MII clock divisor constant for DCR running at 100MHz. */
     99 #define GMI_MGMT_CLKDIV_100MHz 	0x00000028
    100 
    101 #define TEMAC_GMI_UNI0 		0x0380 		/* Unicast address word 0 */
    102 #define TEMAC_GMI_UNI1 		0x0384 		/* Unicast address word 1 */
    103 #define TEMAC_GMI_MAT0 		0x0388 		/* Multicast filter word 0 */
    104 #define TEMAC_GMI_MAT1 		0x038c 		/* Multicast filter word 1 */
    105 
    106 #define TEMAC_GMI_AFM 		0x0390 		/* Address filter mode */
    107 #define GMI_AFM_PROMISC 	0x80000000 	/* Promiscuous mode */
    108 
    109 #define TEMAC_GMI_IRQSTAT 	0x03a0
    110 #define TEMAC_GMI_IRQEN 	0x03a4
    111 
    112 #define TEMAC_GMI_MII_WRVAL 	0x03b0 		/* MII write data */
    113 #define TEMAC_GMI_MII_ADDR 	0x03b4 		/* MII address */
    114 #define GMI_MII_ADDR_REG(val) 	((val) & 0x01f)
    115 #define GMI_MII_ADDR_PHY(val) 	(((val) & 0x01f) << 5)
    116 
    117 #endif /*_VIRTEX_DEV_TEMACREG_H_*/
    118