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      1 /* 	$NetBSD: xintcreg.h,v 1.1 2006/12/02 22:18:47 freza Exp $ */
      2 
      3 /*
      4  * Copyright (c) 2006 Jachym Holecek
      5  * All rights reserved.
      6  *
      7  * Written for DFC Design, s.r.o.
      8  *
      9  * Redistribution and use in source and binary forms, with or without
     10  * modification, are permitted provided that the following conditions
     11  * are met:
     12  *
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  *
     16  * 2. Redistributions in binary form must reproduce the above copyright
     17  *    notice, this list of conditions and the following disclaimer in the
     18  *    documentation and/or other materials provided with the distribution.
     19  *
     20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     21  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     22  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     23  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     24  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     25  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     26  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     27  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     28  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     29  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #ifndef	_VIRTEX_DEV_XINTCREG_H_
     33 #define	_VIRTEX_DEV_XINTCREG_H_
     34 
     35 #ifdef	_KERNEL_OPT
     36 #include "opt_xintc.h"
     37 #endif
     38 
     39 #ifndef	DCR_XINTC_BASE
     40 #error "XINTC component DCR base address undefined!"
     41 #endif
     42 
     43 /* Xilinx "XintC" interrupt controller, connects to DCR. */
     44 
     45 #define	XINTC_ISR 	(DCR_XINTC_BASE + 0) 	/* Status (not masked) */
     46 #define	XINTC_IPR 	(DCR_XINTC_BASE + 1) 	/* opt: Pending (masked) */
     47 #define	XINTC_IER 	(DCR_XINTC_BASE + 2) 	/* Enable */
     48 #define	XINTC_IAR 	(DCR_XINTC_BASE + 3) 	/* Acknowledge */
     49 #define	XINTC_SIE 	(DCR_XINTC_BASE + 4) 	/* opt: Set Enable bits */
     50 #define	XINTC_CIE 	(DCR_XINTC_BASE + 5) 	/* opt: Clr Enable bits */
     51 #define	XINTC_IVR 	(DCR_XINTC_BASE + 6) 	/* opt: Vector */
     52 #define	XINTC_MER 	(DCR_XINTC_BASE + 7) 	/* Master enable */
     53 
     54 #define MER_ME 		0x00000001 		/* Master enable */
     55 #define MER_HIE 	0x00000002 		/* Hw intr enable, write once */
     56 
     57 #endif /*_VIRTEX_DEV_XINTCREG_H_*/
     58