1 /* $NetBSD: hd64461intcreg.h,v 1.3 2008/04/28 20:23:22 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _HPCSH_DEV_HD64461INTCREG_H_ 33 #define _HPCSH_DEV_HD64461INTCREG_H_ 34 35 /* Interrupt Request Register */ 36 #define HD64461_INTCNIRR_REG16 0xb0005000 37 #define HD64461_INTCNIRR_PCC0R HD64461_INTC_PCC0 38 #define HD64461_INTCNIRR_PCC1R HD64461_INTC_PCC1 39 #define HD64461_INTCNIRR_AFER HD64461_INTC_AFE 40 #define HD64461_INTCNIRR_GPIOR HD64461_INTC_GPIO 41 #define HD64461_INTCNIRR_TMU0R HD64461_INTC_TMU0 42 #define HD64461_INTCNIRR_TMU1R HD64461_INTC_TMU1 43 #define HD64461_INTCNIRR_IRDAR HD64461_INTC_IRDA 44 #define HD64461_INTCNIRR_UARTR HD64461_INTC_UART 45 46 /* Interrupt Mask Register */ 47 #define HD64461_INTCNIMR_REG16 0xb0005002 48 #define HD64461_INTCNIMR_PCC0M HD64461_INTC_PCC0 49 #define HD64461_INTCNIMR_PCC1M HD64461_INTC_PCC1 50 #define HD64461_INTCNIMR_AFEM HD64461_INTC_AFE 51 #define HD64461_INTCNIMR_GPIOM HD64461_INTC_GPIO 52 #define HD64461_INTCNIMR_TMU0M HD64461_INTC_TMU0 53 #define HD64461_INTCNIMR_TMU1M HD64461_INTC_TMU1 54 #define HD64461_INTCNIMR_IRDAM HD64461_INTC_IRDA 55 #define HD64461_INTCNIMR_UARTM HD64461_INTC_UART 56 57 /* common defines. */ 58 #define HD64461_INTC_PCC0 0x4000 59 #define HD64461_INTC_PCC1 0x2000 60 #define HD64461_INTC_AFE 0x1000 61 #define HD64461_INTC_GPIO 0x0800 62 #define HD64461_INTC_TMU0 0x0400 63 #define HD64461_INTC_TMU1 0x0200 64 #define HD64461_INTC_IRDA 0x0040 65 #define HD64461_INTC_UART 0x0020 66 67 #endif /* !_HPCSH_DEV_HD64461INTCREG_H_ */ 68
Indexes created Wed Sep 24 15:09:51 GMT 2025