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      1 # $NetBSD: README.models,v 1.7 2021/05/28 00:18:27 simonb Exp $
      2 
      3 MIPS models and architecture levels
      4 -----------------------------------
      5 
      6 Since this is a complex and confusing topic and there's a shortage of
      7 information (especially, a shortage of reliable information), I'm
      8 creating this document as a reference for people doing MIPS stuff on
      9 NetBSD (and elsewhere).
     10 
     11 Citations appear in []. With luck all important facts have citations.
     12 
     13 
     14 ------------------------------------------------------------
     15 1. Architecture levels.
     16 
     17 These architecture levels exist:
     18 
     19         32-bit     64-bit
     20 
     21         MIPS-I
     22         MIPS-II
     23                    MIPS-III
     24                    MIPS-IV
     25                    MIPS-V
     26         MIPS32     MIPS64
     27         MIPS32r2   MIPS64r2
     28         MIPS32r3   MIPS64r3
     29         MIPS32r5   MIPS64r5
     30         MIPS32r6   MIPS64r6
     31 
     32 Note that while MIPS32 is a 32-bit subset of MIPS64, each
     33 corresponding pair of MIPS32rN and MIPS64rN are comparable in age and
     34 properties. Later revisions (further down the list) are mostly supersets
     35 of earlier revisions, although some exceptions exist.
     36 
     37 
     38 ------------------------------------------------------------
     39 2. CPU models.
     40 
     41 For vintage MIPS these are the standard models as of fall 1996 [idt96
     42 A-198] and the corresponding architecture levels. (There were many
     43 additional models put out by licensees or by the MIPS company itself,
     44 which have model numbers with fewer zeros.)
     45 
     46 	R2000		MIPS-I (32-bit)		[idt96 1-5]
     47 	R3000		MIPS-I (32-bit)		[idt96 1-5]
     48 	R4000		MIPS-III (64-bit)	[idt96 A-197]
     49 	R4200		MIPS-III (64-bit)	[idt96 A-197]
     50 	R4300		MIPS-III (64-bit)	[idt96 A-197]
     51 	R4400		MIPS-III (64-bit)	[idt96 A-197]
     52 	R4600		MIPS-III (64-bit)	[idt96 A-197]
     53 	R5000		MIPS-IV (64-bit)	[idt96 1-5]
     54 	R6000		MIPS-II (32-bit) with 64-bit FPU regs
     55 	R8000		MIPS-IV (64-bit)	[idt96 1-5]
     56 	R10000		MIPS-IV (64-bit)	[idt96 1-5]
     57 	R1x000		MIPS-IV (64-bit)
     58 
     59 For later models than this I currently have no information.
     60 
     61 
     62 ------------------------------------------------------------
     63 3. CPU models present in various systems.
     64 
     65 These are the CPU models found in various systems NetBSD does and
     66 doesn't support. This table also notes endianness; MIPS chips are
     67 bi-endian but are wired up one way or the other on motherboards.
     68 
     69    algor (little-endian [buildsh])
     70 	Algorithmics P-4000i			??
     71 	Algorithmics P-4032			??
     72 	Algorithmics P-5064			??
     73 	Algorithmics P-6032			??
     74    arc (little-endian [buildsh])
     75 	Acer PICA				??
     76 	MIPS Magnum 4000			??
     77 	NEC Image RISCstation			??
     78 	NEC Express RISCserver			??
     79 	NEC RISCserver 2200			??
     80 	NEC RISCstation 2200			??
     81 	NEC RISCstation 2250			??
     82 	NEC Express5800/230 R4400 PCI		presumably R4400 (MIPS-III)
     83 	NEC Express5800/240 R4400 EISA		presumably R4400 (MIPS-III)
     84 	DeskStation Tyne			??
     85    cobalt (little-endian [buildsh])
     86 	Qube ... ??				??
     87 	RaQ ... ??				??
     88    emips (big-endian [buildsh])
     89 	... ??					??
     90 	(see http://research.microsoft.com/en-us/projects/emips/ )
     91    evbmips
     92    	Loongson 2F ( gdium, lemote etc. )	more or less LE MIPS-III with
     93    						some extensions
     94    	xburst ( as in, jz4780, found on CI20 )	LE MIPS32R2 with extensions
     95 	... ??					?? (various-endian)
     96    ews4800mips (big-endian [buildsh])
     97 	EWS4800/350				??
     98 	EWS4800/350F				??
     99 	EWS4800/360AD				??
    100 	EWS4800/360ADII				??
    101 	EWS4800/360SX				??
    102 	EWS4800/360EX				??
    103 	EWS4800/360				??
    104 	... ??					??
    105    hpcmips (big-endian [buildsh])
    106 	see http://wiki.netbsd.org/ports/hpcmips/processor_comparison/
    107    mipsco (big-endian [buildsh])
    108 	Various MIPS Computer Systems, Inc.	see [mipscolist]	
    109 	Bull DPX/Prostation M-20		??
    110    newsmips (big-endian [buildsh])
    111 	NWS-3470D				R3000 (MIPS-I) [portpage]
    112 	NWS-3410				R3000 (MIPS-I) [portpage]
    113 	NWS-3460				R3000 (MIPS-I) [portpage]
    114 	NWS-3710				R3000 (MIPS-I) [portpage]
    115 	NWS-3720				R3000 (MIPS-I) [portpage]
    116 	NWS-3800 series				??
    117 	NWS-4000 series				R4600 (MIPS-III) [portpage]
    118 	NWS-5000				R4[04]00 (MIPS-III) [portpage]
    119    playstation2 (little-endian [buildsh])
    120 	playstation2				R5900
    121 	(almost all of MIPS-III + movn/movz) [linux-mips wiki R5900]
    122    pmax (little-endian [buildsh])
    123 	DECstation/system 2100 and 3100		R2000 (MIPS-I) [portpage]
    124 	DECsystem 5100				R3000 (MIPS-I) [portpage]
    125 	Personal DECstation 5000/20, /25, /33	R3000 (MIPS-I) [portpage]
    126 	Personal DECstation 5000/50		R4000 (MIPS-III) [portpage]
    127 	DECstation/system 5000/120, /125, /133	R3000 (MIPS-I) [portpage]
    128 	DECstation/system 5000/150		R4000 (MIPS-III) [portpage]
    129         DECstation/system 5000/200		R3000 (MIPS-I) [portpage]
    130 	DECstation/system 5000/240		R3000 (MIPS-I) [portpage]
    131 	DECstation/system 5000/260		R4400 (MIPS-III) [portpage]
    132 	DECsystem 5900				R3000 (MIPS-I) [portpage]
    133 	DECsystem 5900-260			R4400 (MIPS-III) [portpage]
    134 	DECsystem 5500				R3000 (MIPS-I) [portpage]
    135    sbmips
    136 	BCM91250A (Swarm) evaluation board	Broadcomm BCM1250 [portpage]
    137    sgimips (big-endian [buildsh])
    138 	4D/20					??
    139 	4D/25					??
    140 	Indigo					R3000 (MIPS-I) [portpage]
    141 	Indigo (R4x00)				R4?00 (MIPS-III) [portpage]
    142         4D/30					??
    143 	4D/35					??
    144         Indigo2 (R4x00)				R4?00 (MIPS-III) [portpage]
    145         Challenge M				??
    146         Indy (R4x00)				R4?00 (MIPS-III) [portpage]
    147         Indy (R5000)				R5000 (MIPS-IV) [portpage]
    148         Challenge S (R4x00)			R4?00 (MIPS-III) [portpage]
    149 	Challenge S (R5000)			R5000 (MIPS-IV) [portpage]
    150 	R10000 Power Indigo2			R10000 (MIPS-IV) [portpage]
    151 	Octane					R1x000 (MIPS-IV) [portpage]
    152         O2 (R5000)				R5000 (MIPS-IV) [portpage]
    153 	O2 (RM5200)				RM5200 (MIPS-IV) [portpage]
    154 	O2 (R7000)				R7000  (MIPS-IV) [portpage]
    155 	O2 (R10000)				R10000 (MIPS-IV) [portpage]
    156 	O2 (R12000)				R12000 (MIPS-IV) [portpage]
    157 	O2 (R14000)				R14000 (MIPS-IV) [portpage]
    158 	Fuel					R1x000 (MIPS-IV) [portpage]
    159 	Tezro					R1x000 (MIPS-IV) [portpage]
    160 	... ??
    161 
    162 
    163 ------------------------------------------------------------
    164 4. FPU properties
    165 
    166 TBD... this is complex and messy (XXX / ??)
    167 
    168 
    169 ------------------------------------------------------------
    170 5. Exception handling properties
    171 
    172 TBD... (XXX / ??)
    173 
    174 
    175 ------------------------------------------------------------
    176 6. MMU properties
    177 
    178 TBD... (XXX / ??)
    179 
    180 
    181 ------------------------------------------------------------
    182 7. Cache properties
    183 
    184 TBD... (XXX / ??)
    185 
    186 
    187 ------------------------------------------------------------
    188 8. Instruction ordering properties and hazards
    189 
    190 TBD... (XXX / ??)
    191 
    192 In the absence of the SYNC instruction before MIPS-II [idt96 A-172,
    193 mips32insn 215], apparently on a R3000 you can force pending memory
    194 writes to complete by doing an uncached read. [idt96 11-13]
    195 
    196 Apparently also on some models but not others the state of the write
    197 buffer is wired to the coprocessor 0 condition bit and you can also do
    198 this by using the otherwise useless bc0f instruction (branch on
    199 coprocessor 0 false) to loop. [no citation, I found this in passing
    200 the other day with Google while looking for something else]
    201 
    202 
    203 ------------------------------------------------------------
    204 9. Pipeline hazards
    205 
    206 TBD... (XXX / ??)
    207 
    208 On MIPS-I a load instruction requires an explicit one-cycle wait
    209 before using the result. This restriction was lifted in MIPS-II,
    210 with the addition of an interlock in the pipeline. [idt96 A-2]
    211 
    212 A multiply should not be started within two cycles of a MFHI or MFLO
    213 instruction, as an interrupt that requires restarting the MFHI or MFLO
    214 might (will) get the result from the subsequent multiply. At least on
    215 MIPS-I. [idt96 2-4]  I guess this is true for divides as well.
    216 
    217 
    218 ------------------------------------------------------------
    219 10. Coprocessor 0 hazards
    220 
    221 TBD... (XXX / ??)
    222 
    223 
    224 ----------------------------------------------------------------------
    225 11. Deprecated/removed material.
    226 
    227 When the exception handling model was changed for MIPS-III
    228 (introducing the ERET instruction) the RFE instruction supporting the
    229 old model was removed.  [idt96 A-134]
    230 
    231 Coprocessor 3 (that is, the ability to have a third coprocessor, which
    232 had never been used for anything) was removed in MIPS-III [idt96 A-197].
    233 
    234 The branch likely instructions (e.g. BEQL) were added in MIPS-II
    235 [mips32insn 56] and deprecated not long after, at least by MIPS32
    236 [mips32insn 57] and were removed in release MIPS32 Release 6
    237 [mips32newinsn2a 71].
    238 
    239 SSNOP as a special NOP was deprecated in MIPS32/64 Release 6
    240 [mips32newinsn2a 375] and sequences using SSNOP should include the
    241 new EHB which counts as an SSNOP on older implementations
    242 [mips32newinsn2a 174] ... and possibly SYNC/SYNCI ???
    243 [mips32newinsn2a 394-401]
    244 
    245 ... ??
    246 
    247 ------------------------------------------------------------
    248 12. Conditional compilation in NetBSD
    249 
    250 TBD... (XXX / ??)
    251 
    252 
    253 ------------------------------------------------------------
    254 References:
    255 
    256 [buildsh] The MACHINE/MACHINE_ARCH architecture table in NetBSD
    257 	build.sh.
    258 
    259 [idt96] "IDT MIPS Microprocessor Family Software Reference Manual",
    260 	Integrated Device Technology, Version 2.0, dated October 1996.
    261 
    262 [linux-mips wiki] https://www.linux-mips.org/wiki/
    263 
    264 [mips32intro] "MIPS32(TM) Architecture For Programmers Volume I:
    265 	Introduction to the MIPS32(TM) Architecture", MIPS
    266 	Technologies, Document Number MD00082, Revision 0.95, dated
    267 	March 2001. This was apparently an external review version or
    268 	something and has been available on the Internet; the final
    269 	version, and later revisions, never were. (AFAIK)
    270 
    271 [mips32insn] "MIPS32(TM) Architecture For Programmers Volume II: The
    272 	MIPS32(TM) Instruction Set", MIPS Technologies, Document Number
    273 	MD00086, Revision 0.95, March 12, 2001. Ditto.
    274 
    275 [mips32newinsn2a] "MIPS32(R) Architecture For Programmers Volume II-A:
    276 	The MIPS32(R) Instruction Set Manual", Imagination, Document
    277 	Number MD00086, Revision 6.02, dated December 10, 2014.
    278 
    279 [mips32priv] "MIPS32(TM) Architecture For Programmers Volume III: The
    280 	MIPS32(TM) Privileged Resource Architecture", Document Number
    281 	MD00090, Revision 0.95, dated March 2001. Ditto.
    282 
    283 [portpage] The port page for this NetBSD port on wiki.netbsd.org, or a
    284 	subpage. Ideally these references should be replaced with
    285 	something less self-referential.
    286 
    287 [mipscolist] List of MIPS Computer Systems, Inc. machines hosted on the
    288 	NetBSD web server: https://www.netbsd.org/ports/mipsco/models.html
    289 
    290