1 /* $NetBSD: arpci.c,v 1.7 2021/08/07 16:18:58 thorpej Exp $ */ 2 /*- 3 * Copyright (c) 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Matt Thomas of 3am Software Foundry. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 33 __KERNEL_RCSID(0, "$NetBSD: arpci.c,v 1.7 2021/08/07 16:18:58 thorpej Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 39 #include <dev/pci/pcivar.h> 40 41 #include <mips/locore.h> 42 43 #include <mips/atheros/include/arbusvar.h> 44 #include <mips/atheros/include/ar9344reg.h> 45 46 #define PCI_CMD_CFG_READ 0xa 47 #define PCI_CMD_CFG_WRITE 0xb 48 49 struct arpci_softc { 50 device_t sc_dev; 51 bus_dma_tag_t sc_dmat; 52 bus_space_tag_t sc_bst; 53 bus_space_handle_t sc_bsh; 54 struct mips_bus_space sc_memt; 55 struct mips_pci_chipset sc_pc; 56 bool sc_pcie; 57 u_int sc_pba_flags; 58 }; 59 60 static void arpci_bus_mem_init(bus_space_tag_t, void *); 61 62 static void 63 arpci_attach_hook(device_t parent, device_t self, 64 struct pcibus_attach_args *pba) 65 { 66 } 67 68 static int 69 arpci_bus_maxdevs(void *v, int busno) 70 { 71 struct arpci_softc * const sc = v; 72 73 if (busno == 0) 74 return (sc->sc_pcie ? 1 : 22); 75 76 return 32; 77 } 78 79 static pcitag_t 80 arpci_make_tag(void *v, int bus, int dev, int func) 81 { 82 if (bus == 0 && dev == 0) { 83 /* 84 * Local access 85 */ 86 return (func << 8); 87 } 88 89 if (bus == 0 && dev < 21) { 90 /* 91 * Type 0 can only access 21 (32 - 11) devices starting at * device 0 (0 is needed for inbound transactions). 92 * AD[11:32] encodes the idsel for the transaction 93 * (only one bit can be set). 94 * AD[8:11] contains function 95 * AD[2:7] contains the register offset. 96 * AD[0:1] must be zero. 97 */ 98 return (1 << (dev + 11)) | (func << 8); 99 } 100 101 /* 102 * Type 1 Confugration Transaction. 103 */ 104 return (bus << 16) | (dev << 11) | (func << 8) | 1; 105 } 106 107 static void 108 arpci_decompose_tag(void *v, pcitag_t tag, int *busp, int *devp, int *funcp) 109 { 110 if (tag & 1) { 111 if (busp) 112 *busp = (tag >> 16) & 255; 113 if (devp) 114 *devp = (tag >> 11) & 31; 115 } else { 116 if (busp) 117 *busp = 0; 118 if (devp) { 119 if (tag & ~0x7ff) { 120 *devp = ffs(tag >> 11) - 1; 121 } else { 122 *devp = 0; 123 } 124 } 125 } 126 if (funcp) 127 *funcp = (tag >> 8) & 7; 128 } 129 130 static pcireg_t 131 arpci_conf_read(void *v, pcitag_t tag, int reg) 132 { 133 struct arpci_softc * const sc = v; 134 pcireg_t rv = 0xffffffff; 135 136 if ((unsigned int)reg >= PCI_CONF_SIZE) 137 return rv; 138 139 if ((tag & 0x00ff0001) == 1) { 140 KASSERT(((tag >> 11) & 31) > 20); 141 /* 142 * This was a type 0 transaction for a device > 20 which 143 * we can't support. 144 */ 145 return rv; 146 } 147 148 tag |= reg & -4; 149 150 #if 0 151 bus_space_read_4(sc->sc_bst, sc->sc_bsh, AR7100_PCI_ERROR); 152 bus_space_write_4(sc->sc_bst, sc->sc_bsh, AR7100_PCI_ERROR, 153 bus_space_read_4(sc->sc_bst, sc->sc_bsh, AR7100_PCI_ERROR) & 3); 154 #endif 155 156 bus_space_handle_t addr = sc->sc_bsh; 157 if ((tag & ~0x7fe) == 0) { 158 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 159 AR7100_PCI_LCL_CFG_CMD, AR7100_PCI_LCL_CFG_CMD_READ | tag); 160 addr += AR7100_PCI_LCL_CFG_RDATA; 161 printf("%s: tag %#lx: ", __func__, tag); 162 } else { 163 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 164 AR7100_PCI_CFG_ADDR, tag); 165 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 166 AR7100_PCI_CFG_CMD, PCI_CMD_CFG_READ); 167 addr += AR7100_PCI_CFG_RDATA; 168 printf("%s: AD[0:31] 0x%08lx: ", __func__, tag); 169 } 170 171 rv = kfetch_32((void *)addr, 0xffffffff); 172 printf("%#x\n", rv); 173 174 return rv; 175 } 176 177 static void 178 arpci_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data) 179 { 180 struct arpci_softc * const sc = v; 181 182 if ((unsigned int)reg >= PCI_CONF_SIZE) 183 return; 184 185 if ((tag & 0x00ff0001) == 1) { 186 KASSERT(((tag >> 11) & 31) > 20); 187 /* 188 * This was a type 0 transaction for a device > 20 which 189 * we can't support. 190 */ 191 return; 192 } 193 194 tag |= reg & -4; 195 196 if ((tag & ~0x7fe) == 0) { 197 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 198 AR7100_PCI_LCL_CFG_CMD, AR7100_PCI_LCL_CFG_CMD_WRITE | tag); 199 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 200 AR7100_PCI_LCL_CFG_WDATA, data); 201 } else { 202 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 203 AR7100_PCI_CFG_ADDR, tag); 204 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 205 AR7100_PCI_CFG_CMD, PCI_CMD_CFG_WRITE); 206 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 207 AR7100_PCI_CFG_WDATA, data); 208 } 209 } 210 211 static int 212 arpci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 213 { 214 return EINVAL; 215 } 216 217 static const char * 218 arpci_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len) 219 { 220 snprintf(buf, len, "fixme!"); 221 return buf; 222 } 223 224 static const struct evcnt * 225 arpci_intr_evcnt(void *v, pci_intr_handle_t ih) 226 { 227 return NULL; 228 } 229 230 static void * 231 arpci_intr_establish(void *v, pci_intr_handle_t ih, 232 int ipl, int (*func)(void *), void *arg) 233 { 234 return NULL; 235 } 236 237 static void 238 arpci_intr_disestablish(void *v, void *cookie) 239 { 240 } 241 242 static void 243 arpci_conf_interrupt(void *v, int bus, int dev, int func, int swiz, int *ilinep) 244 { 245 } 246 247 static void 248 arpci_chipset_init(struct arpci_softc *sc) 249 { 250 pci_chipset_tag_t pc = &sc->sc_pc; 251 252 pc->pc_conf_v = sc; 253 pc->pc_attach_hook = arpci_attach_hook; 254 pc->pc_bus_maxdevs = arpci_bus_maxdevs; 255 pc->pc_make_tag = arpci_make_tag; 256 pc->pc_decompose_tag = arpci_decompose_tag; 257 pc->pc_conf_read = arpci_conf_read; 258 pc->pc_conf_write = arpci_conf_write; 259 260 pc->pc_intr_v = sc; 261 pc->pc_intr_map = arpci_intr_map; 262 pc->pc_intr_string = arpci_intr_string; 263 pc->pc_intr_evcnt = arpci_intr_evcnt; 264 pc->pc_intr_establish = arpci_intr_establish; 265 pc->pc_intr_disestablish = arpci_intr_disestablish; 266 267 pc->pc_conf_interrupt = arpci_conf_interrupt; 268 269 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 270 //pc->pc_pciide_compat_intr_establish = arpci_pciide_compat_intr_establish; 271 #endif 272 } 273 274 static int 275 arpci_match(device_t parent, cfdata_t cf, void *aux) 276 { 277 struct arbus_attach_args * const aa = aux; 278 bus_space_handle_t bsh; 279 280 if (strcmp(aa->aa_name, cf->cf_name) != 0) 281 return 0; 282 283 if (bus_space_map(aa->aa_bst, aa->aa_addr, aa->aa_size, 0, &bsh)) 284 return 0; 285 286 bus_space_unmap(aa->aa_bst, bsh, aa->aa_size); 287 288 return 1; 289 } 290 291 static void 292 arpci_attach(device_t parent, device_t self, void *aux) 293 { 294 struct arbus_attach_args * const aa = aux; 295 struct arpci_softc * const sc = device_private(self); 296 297 sc->sc_dev = self; 298 sc->sc_bst = aa->aa_bst; 299 sc->sc_dmat = aa->aa_dmat; 300 sc->sc_pcie = (strcmp(device_cfdata(self)->cf_name, "arpcie") == 0); 301 302 if (bus_space_map(aa->aa_bst, aa->aa_addr, aa->aa_size, 0, 303 &sc->sc_bsh)) { 304 aprint_error(": failed to map registers\n"); 305 return; 306 } 307 308 aprint_normal(": PCI%s bus\n", (sc->sc_pcie ? "-Express x1" : "")); 309 arpci_bus_mem_init(&sc->sc_memt, sc); 310 arpci_chipset_init(sc); 311 312 sc->sc_pba_flags |= PCI_FLAGS_MEM_OKAY; 313 314 struct pcibus_attach_args pba; 315 memset(&pba, 0, sizeof(pba)); 316 317 pba.pba_flags = sc->sc_pba_flags; 318 if (pba.pba_flags & PCI_FLAGS_MEM_OKAY) 319 pba.pba_memt = &sc->sc_memt; 320 pba.pba_dmat = aa->aa_dmat; 321 pba.pba_pc = &sc->sc_pc; 322 pba.pba_bus = 0; 323 324 config_found(self, &pba, pcibusprint, CFARGS_NONE); 325 } 326 327 CFATTACH_DECL_NEW(arpci, sizeof(struct arpci_softc), 328 arpci_match, arpci_attach, NULL, NULL); 329 CFATTACH_DECL_NEW(arpcie, sizeof(struct arpci_softc), 330 arpci_match, arpci_attach, NULL, NULL); 331 332 #define CHIP arpci 333 #define CHIP_LITTLE_ENDIAN /* defined */ 334 #define CHIP_MEM /* defined */ 335 #define CHIP_EXTENT /* defined */ 336 #define CHIP_EX_MALLOC_SAFE(v) true 337 #define CHIP_W1_BUS_START(v) 0x10000000UL 338 #define CHIP_W1_BUS_END(v) 0x16ffffffUL 339 #define CHIP_W1_SYS_START(v) CHIP_W1_BUS_START(v) 340 #define CHIP_W1_SYS_END(v) CHIP_W1_BUS_END(v) 341 342 #include <mips/mips/bus_space_alignstride_chipdep.c> 343
Indexes created Sun Sep 21 18:09:52 GMT 2025